Solve Simple VHDL Problem: Get 20/20 on Exam

[Shahil]

Homework Statement

Hey there ... I got this VHDL problem as an exam question and it kinda freaked me out .. had no idea where to even begin and hence, got like 2 marks out of 20.

I do want to know how to program these though:

Here are the questions:

Homework Equations

Well, it's VHDL .. use what you like I guess .. but keep it simple as possible.

The Attempt at a Solution

My attempt at Q1 (which I think is wrong)

Entity Bus is
Begin
port(write1, write2, write3: in std_logic;
wdata1, wdata2, wdata3: in bit_vector(7 downto 0);
f: out bit_vector(7 downto 0));
-- The f variable is what I think is wrong.
End Bus;

Architecture Behaviour of Bus is
Begin
f <= wdata1 when write1 = "1" else
wdata2 when write2 = "1" else
wdata3 when write3 = "1";
End Behaviour;

--

For Q2 .. I was VERY unsure ... What I did was treat the entire structure as the Entity with the inputs:
io_port_data, address_rf, write_rf
I'm not sure if the control signals (load_accumulator, bus_rf, bus_alu, bus_ioport) are to be declared in the Entity.

What confused me is that this Bus has output ports, unlike the Entity described above. Also, I don't know how to program the the registers. This question made up 20 percent of the exam .. If I did get 20/20 .. I would have passed :( PLEASE help!

 

[llain]

I just started to really learn VHDL, but it seems like there's a lot wrong with this...