Subtraction using 2's complement addition question

[mindauggas]

The problem states: "What Intel x86 instructions would you use to accomplish subtraction using 2’s complement addition? This instruction set has a SUB instruction, but don’t use that; write your own 2’s complement routine instead".

Then the book states the answer:

MOV 51, EDX // copy what’s in 51 to the register
NEG EDX // take 2s complement of register
ADD EDX, 50 // subtract contents of 51 from 52
MOV EDX, 101 // store the result in 101

However it is hard for me to understand waht does this allgorithm do, in particular line 3: it takes some value to the register, take's 2's complement then it adds. But what does the 50 mean? Can anyone explain line 3?

 

[jedishrfu]

when it says what's in 51 it means memory location 51

if your memory was represented by an array in a higher language like java then these statements are equivalent to:

edx=mem[51]; // load edx with the data stored in location 51
edx=-edx; // negate it
edx=edx+mem[50]; // adding in the data stored in location 50
mem[101]=edx; // store the answer in location 101

 

[mindauggas]

when it says what's in 51 it means memory location 51

if your memory was represented by an array in a higher language like java then these statements are equivalent to:

edx=mem[51]; // load edx with the data stored in location 51
edx=-edx; // negate it
edx=edx+mem[50]; // adding in the data stored in location 50
mem[101]=edx; // store the answer in location 101

Yes, it seems that I have understood this correctly. The thing I don't understand is the comment in the book in line 3: " subtract contents of 51 from 52" - the "52" should be considered a typo you think?

 

[rcgldr]

Yes, it seems that I have understood this correctly. The thing I don't understand is the comment in the book in line 3: " subtract contents of 51 from 52" - the "52" should be considered a typo you think?

Yes, the 52 is a typo, and also the code is inconsistent in which operand is source and which operand is destination.

For Intel and Microsoft X86 assemblers, the order for a two operand instruction is <destination>, <source>. Also memory reference operands using absolute address will normally specify a segment register, such as ds:0100h. The brackets are optional, such as ds:[0100h].

In addition, EDX is a 4 byte register, so loading and storing at 50 and 51 mean that the operands are overlapping in memory.

 

[Mark44]

The problem states: "What Intel x86 instructions would you use to accomplish subtraction using 2’s complement addition? This instruction set has a SUB instruction, but don’t use that; write your own 2’s complement routine instead".

Then the book states the answer:

MOV 51, EDX // copy what’s in 51 to the register
NEG EDX // take 2s complement of register
ADD EDX, 50 // subtract contents of 51 from 52
MOV EDX, 101 // store the result in 101

Whoever wrote this code is not very familiar with the Intel x86 instruction set.

 

[mindauggas]

Yes, the 52 is a typo, and also the code is inconsistent in which operand is source and which operand is destination.

For Intel and Microsoft X86 assemblers, the order for a two operand instruction is <destination>, <source>. Also memory reference operands using absolute address will normally specify a segment register, such as ds:0100h. The brackets are optional, such as ds:[0100h].

In addition, EDX is a 4 byte register, so loading and storing at 50 and 51 mean that the operands are overlapping in memory.

Thanks, that was really helpfull :)