Understanding CPU Frequency Waveforms and Dead Time in Modern Processors

[artis]

There was a thread recently in another subforums where a user talked about creating "square waves" at Ghz frequencies. It was said there that at that frequency range one cannot have a square wave as the inductance "rounds off" the edges making the waveform sine like.
I am wondering then how about modern CPU's running at a few Ghz typically, what is the waveform like for them and how does the dI/dt look like?

what are the typical "dead time" between pulses as I read that increasing the clock frequency usually makes the CPU to crash due to the fact that the previous pulse hasn't settled yet "waveform dropped to zero", while the next pulse is already rising which disrupts the binary code as the states of transistors overlap, this sounds somewhat similar to a condition known as "shoot through" in switch driven power supplies (smps) where both/all switches conduct at the same time due to the overlapping of their conduction time.

 

[Baluncore]

A CPU running at a few GHz will have gate delays of about 10 picosec so there is plenty of time for the chains of gates to complete before the next clock phase. Most clocks inside a CPU are two phase clocks, not simple square waves with edge triggered registers.

Shoot through current is not the problem. The problem is that every transition must charge or discharge a capacitor. The gate capacitance of the CMOS inputs must be charged by the CMOS output current, so everything internal becomes a trapezoidal wave. The resulting charge flow is power supply current. That higher current heats the chip to the point where the safety margins are reduced and faults start to occur.

The reason why over-clocked CPUs crash is simply because a previous instruction has not completed before the state of the machine is changed for the next instruction.

 

[berkeman]

this sounds somewhat similar to a condition known as "shoot through" in switch driven power supplies (smps) where both/all switches conduct at the same time due to the overlapping of their conduction time.

In addition to Baluncore's reply, as IC feature sizes ("geometry") get smaller and smaller, the leakage current in each cell becomes a greater fraction of the power consumption. The shrinking gate sizes let you drive the gates faster, but there comes a time when the increasing leakage current becomes about the same as the clocking currents $C \frac{dv}{dt}$

 

[artis]

The shrinking gate sizes let you drive the gates faster, but there comes a time when the increasing leakage current becomes about the same as the clocking currents

So there is a point where the "sweet spot" of nm die size is hit, I would say we are already there or maybe even a little past are we not?

 

[Baluncore]

I would say we are already there or maybe even a little past are we not?

We have always been there. The "sweet spot" as you call it, moves with time.