Where is an ISR stored? Estimated time taken to address an interrupt

[PainterGuy]

Hi,

I'd really appreciate it if you could help me with the queries below.

I think that the quoted text below at the bottom is a very simplified way of describing what happens when an interrupt happens. I believe that in reality the process would be more complex. The processor needs to store information from general purpose registers, ALU registers, and do many other dozens of things before it proceeds to Interrupt Vector Table or Interrupt Service Routine (ISR). ISR is also called Interrupt Handler.

Question 1:
I think that the order and number of activities any processor needs to perform before executing ISR would vary from one microcontroller to another. For example microcontroller 8051 might handle interrupts differently from PIC16f876. Please correct me if I'm wrong.

Question 2:
I'm sure each processor has a fixed set of hardwired instructions written somewhere which dictates it what to do when an interrupt occurs. What steps it needs to take every time an interrupt occurs before proceeding to ISR. I mean the processor should have some fixed set of instructions which tells which registers it needs to store first and in what order before it heads toward interrupt vector table or ISR. What are these instructions called and where are these stored? In some kind of firmware? Does a microcontroller such as 8051 have any firmware?

Question 3:
Where is the ISR stored is a microcontroller? Is it part of some kind of firmware?

Question 4:
Where can I find an estimated approximate time the processor takes before it addresses an interrupt? I mean how long it takes to store the currently executing instructions, store the information from registers, etc. I was trying to find this information for 8051 micronctroller.

Steps to Execute an Interrupt

When an interrupt gets active, the microcontroller goes through the following steps −

• The microcontroller closes the currently executing instruction and saves the address of the next instruction (PC) on the stack.
• It also saves the current status of all the interrupts internally (i.e., not on the stack).
• It jumps to the memory location of the interrupt vector table that holds the address of the interrupts service routine.
• The microcontroller gets the address of the ISR from the interrupt vector table and jumps to it. It starts to execute the interrupt service subroutine, which is RETI (return from interrupt).
• Upon executing the RETI instruction, the microcontroller returns to the location where it was interrupted. First, it gets the program counter (PC) address from the stack by popping the top bytes of the stack into the PC. Then, it start to execute from that address.

Source: https://www.tutorialspoint.com/embedded_systems/es_interrupts.htm

 

[Tom.G]

They got it mostly right, at least for some processors. As you would expect, details vary by manufacturer and architecture.

• The microcontroller closes the currently executing instruction and saves the address of the next instruction (PC) on the stack.
• It also saves the current status of all the interrupts internally (i.e., not on the stack).
• It jumps to the memory location of the interrupt vector table that holds the address of the interrupts service routine.
  • An incoming Interrupt signal contains the number of the table entry that holds the address of the desired routine.
• The microcontroller gets the address of the ISR from the interrupt vector table and jumps to it.
  • Conceptually, this is an indirect, indexed, load of the Program Counter (PC) from the Interrupt Vector Table.
• It starts to execute the interrupt service subroutine, which is RETI (return from interrupt).
  • The first instructions in the ISR save any registers it will use. The last instructions in the routine will restore those registers. Most modern processors save the registers on the Stack, some early processors stored the registers in a data area of the Interrupt Routine memory.
  • The Interrupt Routine ends with a RETI instruction, which is a RET instruction with the added feature of re-enabling Interrupts for others to use.
• Upon executing the RETI instruction, the microcontroller returns to the location where it was interrupted. First, it gets the program counter (PC) address from the stack by popping the top bytes of the stack into the PC. Then, it start to execute from that address.

Note that it is the ISR that saves and restores registers. It would be wasteful for the CPU to automatically save all the registers for every Interrupt when only a few registers may be needed.

Anyhow that's the basics. Most processors these days can handle multiple Interrupts interrupting each other, based on a priority hierarchy defined at the system implementation level.

Hope this helps.

Cheers,
Tom

edit: If you want to dig deeper, here is a link to the technical reference for the intel 8080 CPU, circa 1973, the great-grand-daddy of the Intel CPU's in present-day home computers.
http://bitsavers.trailing-edge.com/...Microcomputer_Systems_Users_Manual_197509.pdf
The hardware aspects of Interrupts are on pg 2-11 of the manual, pdf pg 25.

 

[PainterGuy]

Thank you!

It was really helpful.

I'm still looking for the answer to the following question. Where is the ISR stored in a microcontroller? Is it part of some kind of firmware?

The quoted text in my previous post also says the following.

• It also saves the current status of all the interrupts internally (i.e., not on the stack).

What's the purpose of specifically saying "not on the stack"?

 

[rcgldr]

Some processors, such as ARM, don't perform any stack operations, instead a partial register bank switch occurs, and the return address is stored in a (banked) register.

IBM 360/370 mainframes used four 32 bits words of storage for each interrupt. Two of the words were written to with the current state of the cpu, and the other two words were read from to change state to process the interrupt.

 

[Tom.G]

I'm still looking for the answer to the following question. Where is the ISR stored in a microcontroller? Is it part of some kind of firmware?

An ISR is just a program written as a subroutine, with the register saves/recovery tacked on, then ended with a RETI instruction instead of RET. It can be located anywhere in program memory.

Some application programs include one or more ISR's if they are interacting with devices that require attention at unknown times. For instance if you have an audio player that needs to also display the time of day, there may be an ISR included that displays and updates the time. This could be implemented by setting a hardware timer that may be part of the computer system, to trigger an interrupt every second to update an on-screen clock.

A printer driver typically uses an ISR to send the next character when the printer signals it has finished processing the previous character and is ready for the next one. In this case the ISR may be supplied as part of the Operating System, if there is one.

And the computer you are using to read this uses an ISR to read the keyboard, and the mouse if there is one. There would be no point to be constantly asking if the keyboard or mouse needs attention, the computer can do several screen updates (or thousands to millions of calculations) between keystrokes.

Cheers,
Tom

 

[PainterGuy]

An ISR is just a program written as a subroutine, with the register saves/recovery tacked on, then ended with a RETI instruction instead of RET. It can be located anywhere in program memory.

Thank you.

So, I think that an ISR is inserted by the compiler into the final code ready to be burnt into program memory; assuming that the written program code uses interrupt(s).

 

[Tom.G]

Yup.
But in may take some assembly language stuff to populate the Interrupt Vector Table and tell the CPU to recognoze Interrupts. Not all compilers have facility for that.