When an SRAM is power - uped what state do its locations have?

In summary, the conversation discusses the use of SRAM as an entropy source for random number generation. It is mentioned that the contents of SRAM cells are usually either high or low during power-up, but there can also be a small number of cells that are randomly in a state of 1 or 0 due to thermal noise. It is also noted that software tools may default to zeroing all memory in the run-time startup module, but there are options available to prevent this.
  • #1
dexterdev
194
1
Hi PF,
I am searching for a good entropy source for random number generation. I want to know if when an SRAM is powered will its all contents be high(1) or low (0) or do it contain random bits unpredictable.

-Devanand T
 
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  • #2
I think that is up to the manufacturer. However, I do believe that it will be either High or Low. I don't think you will find one where it is random however.
 
  • #3
dexterdev said:
Hi PF,
I am searching for a good entropy source for random number generation. I want to know if when an SRAM is powered will its all contents be high(1) or low (0) or do it contain random bits unpredictable.

-Devanand T

The memory cells are designed to be identical during the manufacturing process but small variations in the process across even a small die will generate a small bias in most cells that will normally cause them to be a 1 or 0 during power-up but usually there is also a sizable number of cells that are close to a state balance that can randomly be a 1 or 0 due to thermal noise or other random events.

http://www.cs.umass.edu/~kevinfu/papers/holcomb-FERNS-IEEE-Computers.pdf
 
Last edited:
  • #4
Thanks for the reply... :)
 
  • #5
Something you have to watch out for when looking for random bits in SRAM is the default actions of the software tools. The usual default is to zero all memory in the run-time startup module but most embedded software systems will have a option in the linker not to zero or initialize memory on power up.
 
  • #6
Thank you for the tip...:smile:
 

1. What is the default state of an SRAM when it is powered up?

The default state of an SRAM when it is powered up is undefined, meaning that the data stored in its locations cannot be predicted or guaranteed to be consistent.

2. Can the state of an SRAM be controlled during power-up?

No, the state of an SRAM cannot be controlled during power-up. It is determined by various factors such as the specific design of the SRAM and the power supply conditions.

3. How does the power-up state of an SRAM affect its functionality?

The power-up state of an SRAM can affect its functionality as it may result in unpredictable data being stored in the locations. This can lead to errors and can potentially cause the SRAM to function incorrectly.

4. Is there a way to ensure a specific power-up state for an SRAM?

Yes, some SRAM designs include power-up reset circuits that can be used to ensure a specific state during power-up. However, this may add complexity and cost to the design.

5. Can the power-up state of an SRAM be changed after the initial power-up?

Yes, the power-up state of an SRAM can be changed after the initial power-up by writing new data to its locations. However, this can only be done if the SRAM is functional and accessible.

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