Recent content by reddvoid
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Does PhysicsForums have an official mobile app?
Does PhysicsForums have an official mobile app ?- reddvoid
- Thread
- Replies: 2
- Forum: Feedback and Announcements
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What is AP layer in Ansys RedHawk?
Its Auto Pad connection layer- reddvoid
- Post #2
- Forum: Electrical Engineering
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What is AP layer in Ansys RedHawk?
What is AP layer in ansys redhawk ? I have list of layers I see in ansys redhawk tool, there are different metal and via layers , instances etc and there is a layer called AP in the end, What is this layer or where can I find more information bout it?- reddvoid
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- Ansys Ap Power Vlsi
- Replies: 1
- Forum: Electrical Engineering
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Energy consumed in a digital circuit
Hi anorlunda, I did not understand how the units are wrong. P=VI = V (dQ/dt) P dt = V dQ = watts second Watts = Joules/second so dQ * V should give me Joules ; that is Energy so, my statement --> " the total charge*V supposed to give me total energy consumed by the circuit " ...seems to be...- reddvoid
- Post #3
- Forum: Electrical Engineering
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Energy consumed in a digital circuit
I have a digital circuit , to find the energy consumed by the circuit, I am monitoring the current drawn from the supply and integrating it to get the charge pumped into the circuit ... and the total charge*V supposed to give me total energy consumed by the circuit. But I am getting a small...- reddvoid
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- charge circuit current digital energy
- Replies: 9
- Forum: Electrical Engineering
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Synopsys ICC: cell stats and post route netlist from mwlib
Hi, I got the problem solved The command "report_design_physical -all -verbose" did the work Thank you- reddvoid
- Post #3
- Forum: Electrical Engineering
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Synopsys ICC: cell stats and post route netlist from mwlib
Hi, I have loaded the milkyway database of the design to the synopsys ic compiler how can i get details of all the cells present in the design or the netlist after place and route ? Thanks :)- reddvoid
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- Cell Stats
- Replies: 1
- Forum: Electrical Engineering
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Input capacitance discrepancy -- schematic post layout and parasitic capacitance
I am measuring cap by giving a ramp voltage to the pin getting the charge delivered and dividing it by voltage final value. Thanks for the SPF info. didn't know about this, but what would be the percent of cap due to this new nets introduced compared to total parasitic cap ?- reddvoid
- Post #3
- Forum: Electrical Engineering
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Input capacitance discrepancy -- schematic post layout and parasitic capacitance
Hi, I have a post layout extracted netlist, In which I am interested in input capacitance on clock pin, If i measure clock pin input capacitance on post layout extracted netlist, I am getting 1.58fF and when I measure the same in schematic, I am getting 0.6fF and I am able to find the paracitics...- reddvoid
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- Capacitance Circuit Circuit design Input Schematic
- Replies: 2
- Forum: Electrical Engineering
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Undergrad Most effective of 1000 groups given mean median mode and N
@mfb Hi, Like this there are thousands of paths with different cells .- reddvoid
- Post #6
- Forum: Set Theory, Logic, Probability, Statistics
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Undergrad Most effective of 1000 groups given mean median mode and N
In the example I gave, by most critical I meant the one which is contributing most to the total delay in general, Frequency is number of times each cell(or stop) is appearing and I gave 1000 times just for example , In the data I have, as you can see the frequencies are different for different...- reddvoid
- Post #4
- Forum: Set Theory, Logic, Probability, Statistics
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Undergrad Most effective of 1000 groups given mean median mode and N
Hi, For a SoC project I am working on I need to select one cell which is most critical. example, If a bus is going through 1000 stops 1000 times I have mean median mode of delay contribution of that stop compared to the total delay to reach from start to stop point and N (number of times bus...- reddvoid
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- Frequency Groups Mean Median Mode
- Replies: 6
- Forum: Set Theory, Logic, Probability, Statistics
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What is the function of this 6 volt timer and motor control circuit?
No attachment- reddvoid
- Post #3
- Forum: Electrical Engineering
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Cadence Inverter layout lambda based design
I am creating layout of cmos inverter in cadence virtuoso using 0.18um technology. channel length is 2Lambda = 0.18um I read that contact should be 2Lamda X 2Lambda that is 0.18um X 0.18um right but my LVS Check is throwing error telling that contact must be 0.22umX0.22um whats might be the...- reddvoid
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- Design Inverter Lambda
- Replies: 1
- Forum: Electrical Engineering
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Capacitances in NAND2 depletion mode nmos logic
Why we are not writing Cgs Cdb in depletion mode nmos here why no Csb in bottom nmos Can somebody please explain how to write which components of Cload or provide some links from where i can understand it better thank you, this picture is from...- reddvoid
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- depletion Logic Mode
- Replies: 1
- Forum: Electrical Engineering