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Input capacitance discrepancy -- schematic post layout and parasitic capacitance

  1. Oct 4, 2016 #1
    I have a post layout extracted netlist, In which I am interested in input capacitance on clock pin,
    If i measure clock pin input capacitance on post layout extracted netlist, I am getting 1.58fF
    and when I measure the same in schematic, I am getting 0.6fF
    and I am able to find the paracitics in the clock pin to be 0.4fF (from .spf file)

    so the schematic cap + Parasitic cap. should add up to post layout cap right ?
    I am not able to trace where the remaining 0.58fF coming from in post layout cap.
  2. jcsd
  3. Oct 4, 2016 #2


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    How are you measuring the capacitance in the post-layout extracted netlist? Are you using Calibre PEX? If so you should be aware that often there is more effective capacitance coupled to other nets than ground but often people have the report set up to return capacitance to ground.

    Be aware that looking at the SPF file can be deceiving. Calibre (or similar extraction tools) often introduce new nets into the netlist (for example for series cap structures) and these add up to the total cap on a logical net even though you won't capture them if you just grep for a specific net name.
  4. Oct 6, 2016 #3
    I am measuring cap by giving a ramp voltage to the pin getting the charge delivered and dividing it by voltage final value.
    Thanks for the SPF info. didn't know about this, but what would be the percent of cap due to this new nets introduced compared to total parasitic cap ?
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