Dismiss Notice
Join Physics Forums Today!
The friendliest, high quality science and math community on the planet! Everyone who loves science is here!

Cadence Inverter layout lambda based design

  1. Sep 22, 2014 #1
    I am creating layout of cmos inverter in cadence virtuoso
    using 0.18um technology. channel length is 2Lambda = 0.18um
    I read that contact should be 2Lamda X 2Lambda
    that is 0.18um X 0.18um right
    but my LVS Check is throwing error telling that contact must be 0.22umX0.22um
    whats might be the reason ?
     
  2. jcsd
  3. Sep 22, 2014 #2

    analogdesign

    User Avatar
    Science Advisor

    It depends on the technology. For an older process like 0.18um the kit should be well debugged but maybe you're using a not-well-supported kit (since you're using the lambda rules.

    Making a contact larger than minimum is never a problem so I advise you increase the size of the contact to 0.22umx0.2um to get a clean layout.
     
Know someone interested in this topic? Share this thread via Reddit, Google+, Twitter, or Facebook




Similar Discussions: Cadence Inverter layout lambda based design
  1. Inverter design (Replies: 5)

  2. Inverter Design (Replies: 10)

Loading...