AC termination power calculation

[likephysics]

How do we calculate power dissipation for AC termination on a clock signal?
The resistor is dissipating only at the edges(assuming a square wave).

 

[Baluncore]

You need to know the clock frequency, the amplitude of the signal, and the capacitance.
Charge is pumped through the resistor with each clock transition.
C = Q / V ; Q = C⋅V .
Q = I⋅ t ;

Or you model it with LTspice etc.

 

[Tom.G]

I think that @Baluncore supplied the needed information above, but just in case --
Here is a tutorial site about termination. It is mostly DC coupling but does touch on AC coupling. They offer a free handbook and a Chat link after you read the whole page. Might be useful.
https://www.protoexpress.com/blog/pcb-trace-termination-techniques-to-reduce-signal-reflections/

Cheers,
Tom

 

[DaveE]

If the rise/fall time of the square wave is short compared the the RC time constant, then the energy lost on each edge is the same as the energy change on the capacitor so $P_d = f C \Delta V^2$
https://www.maximintegrated.com/con...snubber-power-loss-estimate-saves-the-day.pdf

PS: This assumes that either the initial voltage or the final voltage is zero. It's really $P_d = f C |(V_1^2- V_2^2)|$. Again, the energy change in the capacitor is also the energy lost.

 

[DaveE]

Or you model it with LTspice etc.

Nope. Not for simple circuits. This is a simple derivation which gives you some insight into what's happening. Also, precise answers are virtually never necessary, for most power calculations you're probably looking for a worst-case analysis. I can memorize this simple answer and do it on a handheld calculator about 1000x as fast as you can set up and run your simulator.

BTW, there is (at least in power supplies, where energy is greater) an interesting question about what is the applied voltage step in resonant edges with overshoot. The snubber is designed to reduce them, but also absorbs extra energy in the process, so it is sometimes (OK, rarely) a recursive problem. Again, IRL you just make a worst-case assumption and verify later.

 

[Baluncore]

I can memorize this simple answer and do it on a handheld calculator about 1000x as fast as you can set up and run your simulator.

If saving power in terminations is your only concern, then go ahead. I believe there are more critical parameters than reducing power consumption, for example, functionality and reliability.

Before I build a lower-power clock distribution system, I simulate it to identify phase shift, and the reduction in noise immunity due to Gibbs effect.

 

[DaveE]

If saving power in terminations is your only concern, then go ahead. I believe there are more critical parameters than reducing power consumption, for example, functionality and reliability.

Before I build a lower-power clock distribution system, I simulate it to identify phase shift, and the reduction in noise immunity due to Gibbs effect.

Yes, a distribution network is a great place to use simulators. But that wasn't the question here.

 

[Vanadium 50]

LTspice etc.

Ick.

That's a little unfair. Tools like LSpice have their utility for sure. But there is a whole generation of freshly minted EEs who can only seem to do Spicy things.

I'm talking about recent grads who did not recognize a big electromagnet as an inductor.

Mech E.s have a similar problem. I had one - who is extremely good - ask me what it means when the FEA said a force was negative: it means that had he build it, it would flip over.

These tools have their uses. But brains have more.

 

[Baluncore]

Yes, a distribution network is a great place to use simulators. But that wasn't the question here.

You answer the question as you interpret it.
I answer the question as I interpret it, as part of a bigger world.
Let the OP decide.

Don't tell others are wrong, because you must be right. Gaslighting members who reply, may make others feel you have a personality disorder.

I suggested a solution and the option; "Or you model it with LTspice etc."
I did not insist that be the first and only way.

Ick.

You need to express yourself more clearly.

 

[DaveE]

...may make others feel you have a personality disorder.

Not the first time I've heard that. LOL. Never the less, ad hominin replies aren't really kosher.

My response was intend to inform the OP and other readers that the solution to the step response of an RC circuit is something that you should learn on paper, not by asking a computer to give you the answer. You are absolutely correct, you could use LTSpice to give you a numerical answer, but I don't think that's great advice for simple problems. I'm sorry we disagree about that, but I don't think I'll take it back.

Yes, BTW, I do have a attitude problem with simulators, in spite of having used them quite a bit. They are best for things that are impossible or really difficult to calculate. Otherwise I think they get in the way of education about the foundations of circuit analysis. Perhaps the OP agrees? IDK.

How do we calculate...

PS: Look up the definition of gaslighting. I'm not trying to change you.

 

[berkeman]

Sorry if this question is a bit more on-topic (but not quite), but have any of you used this type of AC termination? I've only used DC forward terminations when the driver can handle the power, and back-terminations when the driver was low power. If I were going to try to use an AC forward termination with a low-power driver, I'd be worried about the complex nature of the termination vs. the real $Z_0$ of the TL. What considerations do you use in sizing the AC termination capacitor?

 

[DaveE]

Sorry if this question is a bit more on-topic (but not quite), but have any of you used this type of AC termination? I've only used DC forward terminations when the driver can handle the power, and back-terminations when the driver was low power. If I were going to try to use an AC forward termination with a low-power driver, I'd be worried about the complex nature of the termination vs. the real $Z_0$ of the TL. What considerations do you use in sizing the AC termination capacitor?

I guess the point is to save power for low frequency clocks (compared to the transition times)? IDK. That would be the $RC \gg t_r$ case that I mentioned. Most want to move as much data as possible and they end up staring at curvy lines in eye diagrams.

 

[Baluncore]

Sorry if this question is a bit more on-topic (but not quite), but have any of you used this type of AC termination?

Yes, I have used it, but only on low frequency, square-wave heartbeat clocks.
Never use it on digital data, RF signals, nor sinusoidal frequency references.

The RC termination is more of a snubber than a line termination. Changing line length in the future, leads to unpredictable results that are hard to identify.

 

[likephysics]

Sorry if this question is a bit more on-topic (but not quite), but have any of you used this type of AC termination? I've only used DC forward terminations when the driver can handle the power, and back-terminations when the driver was low power. If I were going to try to use an AC forward termination with a low-power driver, I'd be worried about the complex nature of the termination vs. the real $Z_0$ of the TL. What considerations do you use in sizing the AC termination capacitor?

The AC termination is used to terminate DDR4 clock. Other than this, I haven't see AC termination much.
See page 8 of this app note: https://community.nxp.com/pwmxy87654/attachments/pwmxy87654/imx-processors/188384/1/AN5097.pdf
DMM ref designs also have AC termination on the clock.

 

[likephysics]

If the rise/fall time of the square wave is short compared the the RC time constant, then the energy lost on each edge is the same as the energy change on the capacitor so $P_d = f C \Delta V^2$
https://www.maximintegrated.com/con...snubber-power-loss-estimate-saves-the-day.pdf

PS: This assumes that either the initial voltage or the final voltage is zero. It's really $P_d = f C |(V_1^2- V_2^2)|$. Again, the energy change in the capacitor is also the energy lost.

DaveE, thanks for link and the answer. I was trying to use C*V^2*f and then use 20-30% of the result to account for rise and fall time.
There's also power dissipated by the resistor during this duration, right?

 

[likephysics]

You need to know the clock frequency, the amplitude of the signal, and the capacitance.
Charge is pumped through the resistor with each clock transition.
C = Q / V ; Q = C⋅V .
Q = I⋅ t ;

Or you model it with LTspice etc.

I did use LTspice and learnt how to plot power, which I did not know before.
According to simulation, the Ac termination power is 10x lower than just resistor termination for the same freq, amplitude.
I find it that knowing how to do it outside simulation is the key to understanding.

 

[DaveE]

DaveE, thanks for link and the answer. I was trying to use C*V^2*f and then use 20-30% of the result to account for rise and fall time.
There's also power dissipated by the resistor during this duration, right?

This (my) stuff is all about the power dissipated in the resistor. The power loss in the driver is a much different question. Read through that link again, the RC step response should be pretty straight forward. They talk about modifications if you don't meet my $RC \gg t_r$ assumption.