AMD64 why only 8 new GPR and not 16 or 32?

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SUMMARY

The AMD64 architecture extends the x86 instruction set by increasing the number of general-purpose registers (GPR) from 8 to 16. This decision contrasts with RISC architectures like PowerPC, which utilize 32 GPR. The discussion raises questions about why AMD did not further extend the GPR count to 32 or 64, especially considering the Itanium architecture, which features over 100 registers. The AMD64 ISA under "long mode" supports a GPR width of 64 bits, but the limited number of GPR remains a point of contention among developers.

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  • Understanding of x86 and AMD64 architectures
  • Familiarity with general-purpose registers (GPR) and their roles
  • Knowledge of RISC vs. CISC architectures
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Computer architects, systems programmers, and anyone interested in processor design and performance optimization will benefit from this discussion.

ensabah6
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x86 is known to be register-starved, with only 8 GPR

AMD64 extends x86 8 GPR's to 16GPR. Many RISC such as PowerpC uses 32 GPR, which makes me wonder why AMD didn't extend the registers to 32 or even 64 total GPR
(same can be said for SSE, from 8 to 16, why not 32 or 64?) Itanium has over 100
 
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I thought AMD64 ISA under "long mode" with register extensions has a GPR width of 64.

As you prolly know the Itanium is a specialized processor that in itself can cost several hundred dollars.
 

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