Designing Comparator with Discrete BJTs

[likephysics]

Just wondering how would one design a comparator using just discrete BJTs.

 

[uart]

An "emitter coupled pair" makes a simple comparator, but you'd need to include current mirror biasing and an output stage to make anything that even approached the sort of functionality of commercially available IC's.

How simple or how elaborate do you want it?

 

[likephysics]

Emitter coupled pair like the one in attachment?
I've been playing with this since yesterday. How do you fix the gain of this ckt.
In the ckt, how do I overcome the min Vbe requirement of Q1,Q2.

For a TTL output comparator a BJT configured as a CE amplifier with Vcc=5v would work?

I just need something that works and also simple enough to understand.

 

[uart]

You forgot the attachment :)

 

[likephysics]

huh. Here it is.

 

[berkeman]

Emitter coupled pair like the one in attachment?
I've been playing with this since yesterday. How do you fix the gain of this ckt.
In the ckt, how do I overcome the min Vbe requirement of Q1,Q2.

For a TTL output comparator a BJT configured as a CE amplifier with Vcc=5v would work?

I just need something that works and also simple enough to understand.

To make a discrete differential pair, you will usually use a matched transistor pair. There is too much mismatch/offset when you use separate transistors, especially over temperature:

http://www.google.com/imgres?imgurl...en&gbv=2&tbs=isch:1&ei=eYtRTaKcCo72swPtkPy9Bg

.

 

[uart]

huh. Here it is.

Ok I modified your circuit to make about the simplest "comparator" possible out of a few discrete components.

The 10k base resistors will bias the inputs to just below zero volts (about -50mV). It will work better with matched transistors but this is not meant to be a particularly accurate comparator so it doesn’t really matter. It’s definitely only meant as a simple project to explore the most basic aspects of BJT comparator design.

It’s biased so that the output is just off (low) when the two input voltages are at zero and it will switch high when V2 gets about 50mV higher than V1.

Common mode input range is a big problem due to the simple resistor biasing. You might want to explore how you can improve the design with current mirror biasing.

BTW. Q3 could be any general purpose PNP transistor, I just chose the 2N2907A because you seem to be basing other components around the pspice evaluation library.