CMOS Regions of Operation Problem

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tsaitea
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In the attached photo, I found M2 to be triode region b/c the drain and drain source voltage is 0 which will always be less than the output voltage.

However, I am have troubles finding M1's region of operation, VDS >= VGS - VTH.
Vout - Vbias >= Vdd - Vbias - VTH **Vbias = 0.8 V , VTH = 0.5 V.

Vout >= Vdd - VTH

Im at this point now b/c Vout may vary.
 
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  • Circuit schematic of a CMOS common-source stage: PMOS M1 with source to VDD, gate driven by Vin(t) in series with Vbias, and drain at Vout(t) feeding NMOS M2 with its gate and drain tied and source to ground.
    20130307_172920.jpg
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For the moment assume Vin(t) = 0.

For the Fet to be on the gate voltage must be more than Vth below the source. In other words Vbias > Vdd+Vth.
 
You have not stated your problem.

M2 has no effect whatsoever on the output voltage unless the gate breakdown voltages are exceeded.
 
CWatters said:
For the moment assume Vin(t) = 0.

For the Fet to be on the gate voltage must be more than Vth below the source. In other words Vbias > Vdd+Vth.

So assuming Vin = 0, for the FET to be on VGS > VTH.

Where VG = VDD and VS = Vbias therefore,

VDD - Vbias > VTH

Vbias < VDD-VTH

I don't quite see where you got Vbias > Vdd + Vth from :confused:
 
rude man said:
You have not stated your problem.

M2 has no effect whatsoever on the output voltage unless the gate breakdown voltages are exceeded.

Right so for M2 Vout > Vth ,

For triode,

VDS2 < VGS2 - Vth
0 < Vout - Vth and since Vout > Vth,
M2 will be in triode.
 
tsaitea said:
So assuming Vin = 0, for the FET to be on VGS > VTH.

Where VG = VDD and VS = Vbias therefore,

VDD - Vbias > VTH

Vbias < VDD-VTH

I don't quite see where you got Vbias > Vdd + Vth from :confused:

M1 is a P type FET. So if I remember correctly the gate (VDD) has to be below the drain/source for it to be ON. Therefore Vbias must be > Gate + Vth.

M2 appears to be configured as a capacitor.
 
CWatters said:
M1 is a P type FET.

I don't think so. It's an N type.

The more conventional symbol for an N type is an arrow pointing into the substrate, but the alternative symbol is the source pointing away from the device, with no subtrate indicated.
.
 
Darn it you are right. I should have looked more carefully.
 
CWatters said:
Darn it you are right. I should have looked more carefully.

Well, without actual values for the bias and ac inputs the whole business is unsolvable anyway ...