I have attached the picture of the circuit. I'm trying to figure out the steady state voltages across the 2 resistors and the capacitor. V_s is given to be 10V DC. At steady state in a DC circuit, a capacitor acts as an open. When that happens, we shouldn't expect any current to flow through the middle branch right? If so, then that means there would be a 10V drop across 'C' and 0V drop across R_1. R_2 would also experience a 10V drop.