How to Use Two Enable Inputs in a Challenging Decoder Question?

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Discussion Overview

The discussion revolves around the use of two enable inputs in a decoder circuit, specifically focusing on implementation challenges and potential solutions. The context includes technical explanations and suggestions for specific decoder ICs.

Discussion Character

  • Technical explanation
  • Debate/contested

Main Points Raised

  • Some participants express confusion about how to effectively use two enable inputs in a decoder.
  • It is noted that when neither enable input is asserted, all outputs are disabled.
  • One participant suggests studying the 74LS137 3-to-8 decoder as a potential solution for implementation issues.
  • Another participant proposes that the 74xx138 IC might be a more suitable option since the question does not require address latches.
  • A participant acknowledges the suggestion regarding the 74LS137 and thanks the contributor.

Areas of Agreement / Disagreement

There is no clear consensus on the best approach to using two enable inputs, as participants suggest different decoder ICs and express varying levels of understanding regarding the implementation.

Contextual Notes

The discussion does not resolve the specific implementation challenges, and assumptions about the requirements for the decoder are not fully articulated.

tonald
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I have no idea about how to use two "enable inputs". (the second part of the question)
 

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tonald said:
I have no idea about how to use two "enable inputs". (the second part of the question)

When neither of the enable inputs is asserted, all of the outputs are disabled.
 
If you're stuck on implementation, I advise you to study the 74LS137 3-to-8 decoder :)
 
Wo0p said:
If you're stuck on implementation, I advise you to study the 74LS137 3-to-8 decoder :)

Actually, since the question doesn't require address latches, it might be easier for them to study the 74xx138 IC. Good suggestion, though.

(xx = HC, AC, LS, whatever).
 
berkeman: you're quite right, ty
 

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