Interpreting logic levels for level translator SN54SLC8T245-SEP

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Discussion Overview

The discussion revolves around the interpretation of logic levels and current characteristics for the SN54SLC8T245-SEP level translator, particularly in the context of shifting single-ended signals for SPI interfaces. Participants seek guidance on parameters such as VOH, VOL, IOL, IOH, IIL, and IIH, and their compatibility with various voltage levels.

Discussion Character

  • Technical explanation
  • Conceptual clarification
  • Debate/contested
  • Experimental/applied

Main Points Raised

  • One participant expresses difficulties in interpreting the logic voltage and current characteristics of the SN54SLC8T245-SEP for their specific application, asking for guidance on compatibility between devices.
  • Another participant questions the specificity of the initial inquiry, suggesting that the questions posed do not provide enough detail to warrant a comprehensive response.
  • Some participants confirm the values for VIL (max) and VIH (min) as stated in the datasheet, but express uncertainty about what further information is being sought.
  • A participant mentions that current specifications may not be critical unless there are fan-out issues, and emphasizes the importance of checking input voltage specs for tolerance to higher voltages than Vdd.
  • It is noted that SPI signals are generally uni-directional, which could simplify the choice of level shifters to uni-directional types.
  • Concerns are raised about the speed capability of the level translator, with a reminder to double-check specifications, especially for bi-directional devices.
  • One participant shares a personal experience with a bidirectional translator that had high output impedance and input bias current issues, advocating for the use of simpler, unidirectional translators when possible.

Areas of Agreement / Disagreement

Participants express varying levels of agreement on the interpretation of the datasheet values, but there is no consensus on the specific guidance requested by the original poster. Multiple competing views on the importance of different parameters and configurations remain present.

Contextual Notes

Some assumptions about the application context and device compatibility are not fully articulated, and there are unresolved questions regarding the specific requirements for the level shifting in the participant's setup.

ashah99
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TL;DR
Interpreting logic levels and currents for level translator (VOH, VOL, IOL, IOH, IIL, IIH)
Hello all, I plan on using SN54SLC8T245-SEP for level shifting of single-ended signals from 1.5 V to 1.8 V, 1.5V to 3.3 V, 1.8 V to 1.5V and 3.3V to 1.5V. First time using level translators for mostly SPI interfaces, so I would like some guidance. I am having difficulties interpreting the logic voltage and current characteristics so that I can determine compatibility between devices, specifically the VOH, VOL, IOL, IOH, IIL, IIH, as it pertains to my application. I appreciate any input.

From the datasheet I have determined that the following, which I hope is correct:
VIL (max): 0.63V (Vcc = 1.8V) or 0.8V (Vcc = 3.3V)
VIH (min): 1.17V (Vcc = 1.8V) or 2V (Vcc = 3.3V)

Reference datasheet: https://www.ti.com/lit/ds/symlink/sn54slc8t245-sep.pdf
 
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ashah99 said:
Summary: Interpreting logic levels and currents for level translator (VOH, VOL, IOL, IOH, IIL, IIH)

I am having difficulties interpreting the logic voltage and current characteristics so that I can determine compatibility between devices, specifically the VOH, VOL, IOL, IOH, IIL, IIH, as it pertains to my application. I appreciate any input.
So, you are asking "specifically" about your application, without really telling us what that is. You are also asking "specifically" about 8 different parameters on the data sheet (which, BTW, I didn't read all of). Unfortunately, those questions just aren't specific enough to motivate me to comment. I feel like I'd have to read much of the data sheet to you, which seems pointless. Maybe someone else will; that seems a bit too much like the work I used to get paid to do. Could you ask a more specific question, like these?

ashah99 said:
Summary: Interpreting logic levels and currents for level translator (VOH, VOL, IOL, IOH, IIL, IIH)

VIL (max): 0.63V (Vcc = 1.8V) or 0.8V (Vcc = 3.3V)
Yes, that's what it says.
ashah99 said:
Summary: Interpreting logic levels and currents for level translator (VOH, VOL, IOL, IOH, IIL, IIH)

VIH (min): 1.17V (Vcc = 1.8V) or 2V (Vcc = 3.3V)
Yes, that's what it says.

Sorry, I just don't know what you want to hear about Voh, et. al. It's all in the data sheet, isn't it?
 
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ashah99 said:
Hello all, I plan on using SN54SLC8T245-SEP for level shifting of single-ended signals from 1.5 V to 1.8 V, 1.5V to 3.3 V, 1.8 V to 1.5V and 3.3V to 1.5V. First time using level translators for mostly SPI interfaces, so I would like some guidance.

There are several things to consider in level shifting:
  • The current (input/output) specs don't really enter into this, unless you have fan-out issues, which it does not sound like you do
  • SPI signals are generally uni-directional in the simplest implementation, so if that applies to you, that simplifies the level shifters to being uni-directional
  • Look at the input voltage specs of your devices, to see if they are tolerant of slightly higher voltages than their ##V_{dd}## values. It is common for some 3.3V logic to have inputs that are 5V tolerant, for example. It takes a special IO pad circuit structure to allow these input voltages a bit above the ##V_{dd}## value, but check the datasheet to look for that feature
  • If your devices use CMOS I/O levels, you probably do not need to worry too much about the input/output voltage level specs. It's mainly when you mix TTL and CMOS voltage levels (or more exotic logic like IIL) that you have to worry about logic input/output voltage levels.
  • The speed capability of the voltage level translator device can be important, since some simple ones are pretty slow. It looks from the datasheet like your chosen device should be fast enough for most applications. Always double-check the speed capability when choosing a level translator, though, especially bi-directional ones.
 
berkeman said:
SPI signals are generally uni-directional in the simplest implementation, so if that applies to you, that simplifies the level shifters to being uni-directional
This is very good advice to use the simplest device that works.

I have been burnt by trying to use bidirectional translators. The one I tried to use (TXB0104 if I recall correctly) had a rather high output impedance. The input bias current of one of the devices was just too high. It was a part I had in stock so it seemed the easiest route to the goal. It was just logic level async serial so unidirectional translators fixed it on the next run.

SOP is to roll the dice on a new board and fix it in post. Thankfully this one we got in as a few as prototypes. It would have been a nightmare to have to bodge in a couple hundred TSSOP chips.

BoB
 
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