Makefile in Unix environment: help

  • Thread starter nrqed
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In summary: If everything succeeds, make prints "done".The target rule might be as simple ashello: main.owhich will just compile main.o and put it in the target directory. It is also possible to have more than one target, and to have more than one rule for a target.MacrosMake also provides a facility for defining macros. A macro is just a string of characters surrounded by quotation marks. The rules for Makefile are summarized as follows −If a string is preceded by a "$" sign, it is a shell command.Otherwise, a macro is just a string of characters.A macro can be used in place of a string, but
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nrqed
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NEVER MIND! I finally found a good reference explaining all of this. Sorry for the wasted bandwidth!

Patrick



I have this makefile I am trying to understand.

It goes like this:

COMP = ifort
FLAGS = -autodouble etc...
GLOBALS = a bunch of .o files...


glue: gluon_operators.o
$(COMP) $(FLAGS) -o main_program *.o

gluon_operators.o: gluon_operators.f90 loop_functions.o $(GLOBALS)
$(COMP) $(FLAGS) -c gluon_operators.f90


and so on...

I understand that this is compiling stuff using the Fortran compiler with some flags.

What I am confused about are the lines with a ":", for example

glue: gluon_operators.o

I have no idea what this line does.
Also, the line


gluon_operators.o: gluon_operators.f90 loop_functions.o $(GLOBALS)


is a mystery to me. What does the ":" do?

Also, I don't understand the line with main_program. It seems to me that the -o says to output the result of the compilation to main_program, but there does not seem to be anything compiled in the first place ?! I would have expected $(COMP) $(FLAGS) program.f90 -o main_program or something similar.

Also, what does the "*.o" mean at the end of that same line? It says something about all files ending with .o but I don't quite understand the whole line. Maybe it says that anything that will be compiled next must
put together in the file main_program??


I would really appreciate help!

Patrick
 
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For others who have the same question, I found this reference -- https://www.tutorialspoint.com/makefile/makefile_quick_guide.htm
Defining Rules in Makefile

We will now learn the rules for Makefile.

The general syntax of a Makefile target rule is −
target [target...] : [dependent ...]
[ command ...]

In the above code, the arguments in brackets are optional and ellipsis means one or more. Here, note that the tab to preface each command is required.

A simple example is given below where you define a rule to make your target hello from three other files.
hello: main.o factorial.o hello.o
$(CC) main.o factorial.o hello.o -o hello

NOTE − In this example, you would have to give rules to make all object files from the source files.

The semantics is very simple. When you say "make target", the make finds the target rule that applies; and, if any of the dependents are newer than the target, make executes the commands one at a time (after macro substitution). If any dependents have to be made, that happens first (so you have a recursion).
 

What is a Makefile and how does it work?

A Makefile is a text file that contains a set of instructions, known as rules, for compiling and building a software project. It is used in the Unix environment to automate the process of building executable files from source code. The Makefile works by checking the timestamps of the source files and only recompiling the ones that have been modified since the last build.

How do I create a Makefile?

To create a Makefile, you can use a text editor such as vi or nano to write the necessary rules and commands. Each rule consists of a target, dependencies, and a set of commands to be executed. Once the Makefile is saved, you can use the "make" command in the terminal to execute it and build your project.

What are the advantages of using a Makefile?

Makefiles offer several advantages in the Unix environment. They allow for the automation of the build process, making it more efficient and less error-prone. Makefiles also make it easier to manage complex software projects with multiple source files and dependencies. Additionally, they can be easily modified and reused for different projects.

How do I debug errors in my Makefile?

If your Makefile is not working as expected, you can use the "-d" flag when running the "make" command to enable debugging. This will provide more detailed information about the build process, including any errors or warnings. Additionally, you can use the "-p" flag to print out the entire Makefile database, which can help identify any issues.

Can I use variables in my Makefile?

Yes, you can use variables in your Makefile to make it more flexible and reusable. Variables can be defined at the top of the Makefile and then used throughout the rules and commands. This allows you to easily change values such as compiler options or file names without having to modify the entire Makefile.

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