The discussion focuses on MIPS pipelining, specifically analyzing the assembly code involving load and add instructions with and without forwarding. The assembly code provided includes the instructions LW R1, 0(R2), add R4, R3, R1, and add R3, R1, R4. Participants seek clarification on filling the pipelining timeline correctly under both scenarios. Key resources mentioned for further understanding include "MIPS Assembly Language Programming" by Robert Britton and "Computer Organization and Design" by Patterson and Hennessy.
PREREQUISITESStudents and professionals in computer science, particularly those studying computer architecture, MIPS programming, or anyone involved in optimizing instruction execution in pipelined processors.
Are you working from a textbook? There are only two that I am aware of: "MIPS Assembly language Programming," by Robert Britton, and "Computer Organization and Design: The Hardware/Software Interface," by Patterson and Hennessey. Chapter 10 in the Britton book, which I have, discusses pipelined implementations. I don't have the other book, so can't comment on it.jdoe10 said:Homework Statement
Assembly Code:
LW R1, 0(R2)
add R4, R3, R1
add R3, R1, R4
What are the dependencies
Fill the pipelining timeline if:
a. There is forwarding
b. There is no forwarding
Homework Equations
N/A
The Attempt at a Solution
With forwarding attempt:
Without forwarding attempt:
Am I filling the pipelining timeline correctly?