MHB Optimizing Carry-Skip Adders for Minimal Delay

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The discussion focuses on optimizing a 32-bit carry-skip adder to minimize computation delay using individual adders of varying sizes (4, 8, and 12 bits). A formula for optimal adder size is mentioned, suggesting that each adder should ideally be around 4 bits based on the equation m = √(n/2). Participants express uncertainty about incorporating delay factors into their calculations, as the provided formula does not account for specific delays associated with different adder sizes. There is a consensus that a diagram illustrating the adders and their delays would aid in understanding and optimizing the mean computation time. Overall, the goal is to determine the best configuration of adders to achieve minimal delay in the output carry computation.
evinda
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Hello! (Wave)

Let a binary adder carry-skip of $32$ bits, at which the size of the individual adders is not necessarily the same. Suppose that the individual adders are adders spreading carry, and that the skip is not done at the first and at the last individual adder. If we can use 4 individual adders, and the available sizes of adders are 4, 8 and 12 bits, compute the size that each individual adder should have, so that the mean time of the computation of the output carry is minimized, supposing that each circuit of a full adder of 1 bit and each circuit of a multiplexer bring a delay of $2T$ at the computation, while the gates AND of 4,8 and 12 inputs bring a delay of $T, 2T$ and $2T$, respectively, where $T$ is the time of delay of an elementary gate.

Could you give me a hint? :unsure:
 
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Hey evinda!

I'm not all that familiar with carry-skip adders yet, and what their mean time of the computation of the output carry is.
Do you have a formula for that? (Wondering)
And maybe a diagram as an example? (Wondering)

I did find on wiki that the optimal size for the carry-skip adders is $m=\sqrt{\frac n2}$, where $n$ is the total number of bits, and $m$ is the bits of each adder.
So the size of the adders for this problem is probably around $m=\sqrt{\frac {32}2}=4$. That is 8 adders of size 4. :unsure:
 
Klaas van Aarsen said:
I did find on wiki that the optimal size for the carry-skip adders is $m=\sqrt{\frac n2}$, where $n$ is the total number of bits, and $m$ is the bits of each adder.
So the size of the adders for this problem is probably around $m=\sqrt{\frac {32}2}=4$. That is 8 adders of size 4. :unsure:

At this size is the delay taken into consideration?

Do we have to do that for each available adder? (Thinking)
 
evinda said:
At this size is the delay taken into consideration?
The delays as mentioned in the problem statement have not been taken into account.
Instead it is a formula I found on wiki that makes certain assumptions about the delays.
It also doesn't say how it was optimized, which may be different from the problem statement. :unsure:

evinda said:
Do we have to do that for each available adder?
I think we have to draw a diagram of a couple of adders together, identify where and what the delays are exactly, find the formula for the desired mean, and optimize that formula to be minimal. (Sweating)
 
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