Optimizing Carry-Skip Adders for Minimal Delay

[evinda]

Hello! (Wave)

Let a binary adder carry-skip of $32$ bits, at which the size of the individual adders is not necessarily the same. Suppose that the individual adders are adders spreading carry, and that the skip is not done at the first and at the last individual adder. If we can use 4 individual adders, and the available sizes of adders are 4, 8 and 12 bits, compute the size that each individual adder should have, so that the mean time of the computation of the output carry is minimized, supposing that each circuit of a full adder of 1 bit and each circuit of a multiplexer bring a delay of $2T$ at the computation, while the gates AND of 4,8 and 12 inputs bring a delay of $T, 2T$ and $2T$, respectively, where $T$ is the time of delay of an elementary gate.

Could you give me a hint? :unsure:

 

[I like Serena]

Hey evinda!

I'm not all that familiar with carry-skip adders yet, and what their mean time of the computation of the output carry is.
Do you have a formula for that? (Wondering)
And maybe a diagram as an example? (Wondering)

I did find on wiki that the optimal size for the carry-skip adders is $m=\sqrt{\frac n2}$, where $n$ is the total number of bits, and $m$ is the bits of each adder.
So the size of the adders for this problem is probably around $m=\sqrt{\frac {32}2}=4$. That is 8 adders of size 4. :unsure:

 

[evinda]

I did find on wiki that the optimal size for the carry-skip adders is $m=\sqrt{\frac n2}$, where $n$ is the total number of bits, and $m$ is the bits of each adder.
So the size of the adders for this problem is probably around $m=\sqrt{\frac {32}2}=4$. That is 8 adders of size 4. :unsure:

At this size is the delay taken into consideration?

Do we have to do that for each available adder? (Thinking)

 

[I like Serena]

At this size is the delay taken into consideration?

The delays as mentioned in the problem statement have not been taken into account.
Instead it is a formula I found on wiki that makes certain assumptions about the delays.
It also doesn't say how it was optimized, which may be different from the problem statement. :unsure:

Do we have to do that for each available adder?

I think we have to draw a diagram of a couple of adders together, identify where and what the delays are exactly, find the formula for the desired mean, and optimize that formula to be minimal. (Sweating)