'Output Enable' switch using BJT or FET

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    Bjt Fet Switch
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Discussion Overview

The discussion revolves around designing an output enable circuit using BJTs or FETs, specifically for digital applications involving logic gates and buffers. Participants explore various configurations and requirements for enabling and disabling the output.

Discussion Character

  • Technical explanation
  • Debate/contested

Main Points Raised

  • One participant inquires about the specifics of the circuit, including whether it is analog or digital, voltage levels, output requirements when enabled or disabled, current needs, and frequency of operation.
  • Another participant confirms that the circuit is digital, specifying the high voltage as 3.3V and low voltage as 0V, with a requirement for high voltage when disabled and a current output of 5-10mA at a maximum frequency of 10KHz.
  • Suggestions are made regarding the use of a pnp transistor, with one participant proposing a configuration where the emitter is connected to Vcc, the collector to the logic gate output, and the base connected through a resistor for enable control.
  • Further clarification is sought about the output, with a participant explaining that the output would still be the logic gate output, and discussing the need to check the logic family compatibility regarding being pulled high when the output is low.
  • Concerns are raised about ensuring high impedance when the output is low, suggesting the potential need for an additional transistor in the circuit.

Areas of Agreement / Disagreement

Participants express differing views on the circuit design and the implications of using specific transistor configurations, indicating that multiple competing approaches remain under consideration.

Contextual Notes

Participants have not fully resolved the implications of the logic family compatibility and the specific requirements for high impedance states, leaving some assumptions unaddressed.

likephysics
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How to design a Output enable ckt (like the ones in logic gates and buffers) using a simple component like BJT or FET.
 
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Can you supply some more details?

Is this an analog or digital circuit?
How high is the high voltage out and how low is the low voltage out?
What are the high and low voltage you want to use to enable or disable?
When disabled, do you want a high voltage, low voltage or just high impedance out?
When enabled, how much current do you need at the output?
What is the highest frequency that will be used?
 
Is this an analog or digital circuit?
>>digital
How high is the high voltage out and how low is the low voltage out?
>.3.3V and 0V
What are the high and low voltage you want to use to enable or disable?
>>3.3V and 0V
When disabled, do you want a high voltage, low voltage or just high impedance out?
>> high voltage
When enabled, how much current do you need at the output?
>> 5-10mA
What is the highest frequency that will be used?
>> max 10KHz
 
Have you considered using a pnp transistor with the emitter connected to Vcc, the collector connector connected to the logic gate output and the base connected through a resistor to be your enable control?
 
skeptic2 said:
Have you considered using a pnp transistor with the emitter connected to Vcc, the collector connector connected to the logic gate output and the base connected through a resistor to be your enable control?
Where do I get the output?
 
The output would still be the logic gate output. All the transistor does is pull the output pin high when not enabled. You will need to check the logic family to see if the gate can stand being pulled high when the output is low. If not, you will need another transistor between the output of the gate and the collector to become high impedance at the same time.
 

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