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How to design a Output enable ckt (like the ones in logic gates and buffers) using a simple component like BJT or FET.
The discussion revolves around designing an output enable circuit using BJTs or FETs, specifically for digital applications involving logic gates and buffers. Participants explore various configurations and requirements for enabling and disabling the output.
Participants express differing views on the circuit design and the implications of using specific transistor configurations, indicating that multiple competing approaches remain under consideration.
Participants have not fully resolved the implications of the logic family compatibility and the specific requirements for high impedance states, leaving some assumptions unaddressed.
Where do I get the output?skeptic2 said:Have you considered using a pnp transistor with the emitter connected to Vcc, the collector connector connected to the logic gate output and the base connected through a resistor to be your enable control?