Phase-Locked Loop: Understanding Coherent Demodulation of AM

[cyeokpeng]

Though I have gone through a communications course in EE, I am still very blur about the Phase-locked loop system in performing coherent demodulation of AM signal.

The problem with direct coherent detection straight from the received AM signal from the receiver antennae is that the local oscillator cannot reproduce the exact same carrier frequency to be hecterodyned with the AM signal to bring it back to baseband. Many reasons colud have caused that, for example, the phenomenon of frequency shifting due to relative motion of the Tx or the Rx (What is the name I forgot), etc etc. So there needs to be a negative feedback to ensure the frequency of the local oscillator approaches the frequency of the carrier in the AM signal. But I really do not understand the mathematics analysis of the system. Can anyone give me an insight to that?

 

[chroot]

A phase-locked loop generally consists of at least two parts:

1) A voltage-controlled oscillator (VCO). A higher input voltage results in a higher frequency, for example.

2) A phase detector. This device compares the phase of the received carrier and the oscillator's output, and produces an error signal. The error signal is fed back into the VCO to adjust its frequency.

Many PLLs also include a thrid component:

3) Loop filter. This filter generally is designed for a specific application, and prevents ringing, overshoot, and other unwanted behavior. The loop filter keeps the loop stable.

Keep in mind that a constant phase error corresponds to a simple frequency error. If the received carrier has a higher frequency than the VCO, the phase error will be constantly positive, making the VCO oscillate more rapidly. If the received carrier has a lower frequency than the VCO, the phase error will be constantly negative, making the VCO oscillate more slowly.

- Warren

 

[cyeokpeng]

Mmm, I am a bit clearer now.

Another question, the PLL can be designed to be a first-order PLL or second-order PLL. How do you design such PLL systems such that they have different order transfer function characteristics? I have just learn feedback theory, systems and control course, and I still do not know how to find the transfer function of a system H(s) with a feedback transfer function H1(s).

And what is the meaning of steady state phase error?
My conception of steady-state phase error is the steady state phase error output signal when passed through the PLL system, and since the PLL is designed to be stable (in phase lock), the steady state phase error will be finite, and we can use the final value theorem of Lasplace tranform to work out its steady state phase error value.
Hope I am correct.