Restored Commodore 64 How It's Made Video

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SUMMARY

The discussion centers on the rediscovery of a long-lost video detailing the manufacturing process of the Commodore 64, highlighting advancements in chip assembly techniques. The contributor, a former IBM employee, emphasizes the innovative C4 Flat Pack (C4FP) design, which utilized a ceramic substrate and Hysol sealant for enhanced durability. They also describe the automated processes involved in chip testing, including the use of VLSI test systems and boundary scan technology, which improved yield rates by identifying faulty memory lines. The conversation reflects on the evolution of chip assembly methods and the importance of precision in manufacturing.

PREREQUISITES
  • Understanding of C4 Flat Pack (C4FP) technology
  • Familiarity with VLSI test systems and chip testing methodologies
  • Knowledge of boundary scan technology for logic chip testing
  • Experience with automated assembly processes in electronics manufacturing
NEXT STEPS
  • Research C4 pad technology and its applications in modern chip design
  • Explore the principles of boundary scan testing and its significance in quality assurance
  • Investigate advancements in automated assembly techniques for semiconductor manufacturing
  • Learn about the impact of AC and DC testing on chip yield optimization
USEFUL FOR

Electronics engineers, semiconductor manufacturing professionals, and anyone interested in the historical and technical aspects of chip design and assembly processes.

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Long lost video rediscovered in a Geman broadcast of a Canadian TV show:

 
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Aah! Fond memories! I used to work at IBM where they put the chip on a ceramic substrate. It was a lot more automated than what is in the video.

I started with products similar to these:

memory-modules-w600.jpg

and with the cap on:
s-l400.png

But I spent so much time on the PowerPC600 which was known to us internally as C4FP (C4 Flat Pack):

870%2Fdesktop_8e09ace7-313c-49a1-ae41-59d89785c0d3.jpg

Even if I knew nothing about anything back then, I was impressed with that design compared to the ones above:
  • The pins clipped on the side instead of "nails" going through (hence "flat pack")​
  • The black seam (Hysol) that secured the clips​
  • The protective cap was replaced by a blue liquid cured to form a gel. And it was contained by the Hysol seam!​
Such a smart design. I cut the ceramic to the proper size, put the pins on, and also the Hysol on this product.

There were also versions with a normal cap similar to this one:

s-l1600.jpg

I remember putting the blue sealant on parts like this one too:

ppc-750-g3.jpg

See, there is the side where it is wider? This I where the needle put the liquid and it just went around the chip by capillary action before being cured. It was all a matter of setting the needle in the right place and having the right amount liquid.

And they went back to pins, but they were soldered on instead of pushed through like in the earlier designs. There was even a version with balls which seems a lot smarter and easier to work with.

s-l1600.jpg

Can you imagine a machine was putting the right amount of some soldering paste on each "pad", at the same time, then the columns were put on, and the assembly was sent to the furnace for welding? Seemed a lot easier to clip the pins on the C4FP.

Look at me rambling like an old man.
 
Cool!

I worked in another IBM group that developed VLSI test systems to evaluate the chips while they were still on the wafers. The testers would examine the chips using DC and AC tests at various key temperatures, creating different chip-picking maps. There was a special robotic arm that would position the test head over the chip site and make contact with the c4 pads of the chip for testing.

We were told that one wafer contained all the key chips that an IBM 370 machine needs.

The chips were selected based on the tests they passed and then transferred to multi-chip modules (MCM). They used C4 pad technology to mount them.

In the case of memory chips, AC chip testing revealed bad data lines that were bypassed when chips were selected. This improved yield when a single memory bit was unreliable.

Logic chips were tested using boundary scan technology. Data was loaded into the scan register, and a clock signal pumped it into the chip. The results were read by reading the boundary scan register.

https://en.wikipedia.org/wiki/Boundary_scan
 
The only test I did was a bubble leak test with parts having a ceramic cap similar to this one:

CPU-PCB-1024x426.jpg

The caps came with the sealant already applied on the edges. After being assembled and cured in an oven, we had to manually put them in an aquarium one tray at a time and watch for bubbles coming out.

Before putting them in the oven, all parts were placed in a jig that properly aligned the caps and substrates, and then we had to turn a cam that applied the proper pressure between the parts for curing. One time, I forgot to turn the cam before putting the jig in the oven. I noticed my mistake when taking it out of the oven and notified my boss of my mistake as it was the end of my shift and I wouldn't be the one testing them. The next day, the person who did the test was like: "What did you do?" There was something like 30-40% of them leaking. Oops! It was a good thing that this happened while being with one of the coolest bosses I ever had at that place, who just reassured me by telling me not to worry about it and that mistakes happen.
 

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