Solving SR Latch: Get 2nd Input from NOR Gates

[whitehorsey]

1. http://forum.allaboutcircuits.com/image_cache/httpwww.cs.nyu.educoursesfall00V22.0436001lecturesfigssrlatch.png

Using this image, how would you get the second input if the second input has to come from the output of the nor gates?

 

[NascentOxygen]

Using this image, how would you get the second input if the second input has to come from the output of the nor gates?

I don't understand what you are asking? Do you even understand what you are asking?

The S-R latch is a basic memory cell. S and R cannot* both simultaneously be TRUE. Provided only one of R and S is TRUE, this forces the cell to take up one of two stable memory states. When that input returns to FALSE, meaning both inputs are now FALSE, the cell remembers that last state.

Now, what was your question? http://imageshack.us/a/img402/3247/undecidedg.gif

 

[whitehorsey]

I don't understand what you are asking? Do you even understand what you are asking?

The S-R latch is a basic memory cell. S and R cannot* both simultaneously be TRUE. Provided only one of R and S is TRUE, this forces the cell to take up one of two stable memory states. When that input returns to FALSE, meaning both inputs are now FALSE, the cell remembers that last state.

Now, what was your question? http://imageshack.us/a/img402/3247/undecidedg.gif

Ah my question is because the nor gate needs two inputs what is the other input the one that belongs to the criss crossed line. So if S = 1 what is the other input that is going into the nor gate with it?

 

[aralbrec]

So if S = 1 what is the other input that is going into the nor gate with it?

It doesn't matter. The result out of the NOR gate will be zero.

When S and R are both zero, the output is in a stable state with Q and /Q being complements of each other. If for some reason Q and /Q are the same (both 1 or both 0), the state immediately changes to 1/0 with the fastest NOR gate deciding which will be 1 and which will be 0.

 

[NascentOxygen]

Ah my question is because the nor gate needs two inputs what is the other input the one that belongs to the criss crossed line. So if S = 1 what is the other input that is going into the nor gate with it?

The second input is ¬Q. Maybe it's 1, maybe it's 0. Try both, one at a time.

 

[CWatters]

Ah my question is because the nor gate needs two inputs what is the other input the one that belongs to the criss crossed line. So if S = 1 what is the other input that is going into the nor gate with it?

The short answer is that the other input is Q but its state doesn't matter.

Longer answer...

So you asked what happens with S=1... Follow it around the circuit step by step...

If S=1 then Qbar = 0 whatever the other input is. Draw the truth table for a NOR gate.

Then if R=0 the inputs to the top gate are R=0 and Qbar=0 so the output Q=1.

If Q=1 then the two inputs at the lower gate are S=1 and Q=1 so the output Qbar = 0

If you then set S back to 0 the circuit will stay ("remember") Q=1 and Qbar=0. That's why S stands for "Set". It sets Q=1.

By symetry if you pulse R from 0 to 1 and back you get Q=0, and Qbar = 1 which is why R stands for "Reset".

So the truth table is...

RS Q Qbar
------------
00 Q and Qbar remember their state
01 Q=1, Qbar=0
10 Q=0, Qbar=1

It is possible to have RS=11 in which case Q=0 and Qbar=0 but if RS change back from 11 to 00 at exactly the same time you can't predict how Q and Qbar will end up. If they change at different times the last one remaining at logic 1 "wins".

 

[whitehorsey]

The short answer is that the other input is Q but its state doesn't matter.

The second input is ¬Q. Maybe it's 1, maybe it's 0. Try both, one at a time.

It doesn't matter. The result out of the NOR gate will be zero.

When S and R are both zero, the output is in a stable state with Q and /Q being complements of each other. If for some reason Q and /Q are the same (both 1 or both 0), the state immediately changes to 1/0 with the fastest NOR gate deciding which will be 1 and which will be 0.

Thank You for your responses! So then I tried working on some practice problems I found on the internet but there's one that I'm stuck on.

E Q_t S_t R_t Q_t+1
0 0 0 0 Q_t
...
1 0 0 0 0
1 0 1 1 undefined
1 0 1 0 1
1 1 0 0 Q_t In this problem, you have to solve for Q_t+1.
The answers I got was Q_t whenever the Enable was equal to 0. I also got Q_t with the second one and fourth and fifth one. Yet, the second one is equal to 0, the fourth one is equal 1 and the fifth one is equal to Q_t. (Answers that came with this problem) Why is that?Also, just to make sure if I understand a part about SR Latch is that whenever S and R = 1 the state would always be undefined?

 

[NascentOxygen]

Also, just to make sure if I understand a part about SR Latch is that whenever S and R = 1 the state would always be undefined?

Precisely what state are we talking about?

If your question involves what are the gates' outputs when S=R=1, then you should be able to work that out. What is the output of any NOR gate when an input equals 1?

Maybe your question is about something else?