Understanding Voltage Drops in RCL Circuits

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Homework Help Overview

The discussion revolves around understanding voltage drops in RCL circuits, specifically focusing on the relationships between voltage across the resistor, capacitor, and inductor in a series circuit without a voltage source. Participants explore the implications of the loop rule and the signs of voltage drops in the context of circuit behavior.

Discussion Character

  • Conceptual clarification, Assumption checking, Problem interpretation

Approaches and Questions Raised

  • Participants question the signs of voltage drops across the components in an RCL circuit and whether the absence of a voltage source affects these signs. They also discuss the implications of charging a capacitor and the behavior of current and voltage over time in both DC and AC circuits.

Discussion Status

There is an ongoing exploration of the relationships between voltage drops and the behavior of circuit elements. Some participants provide insights into the conventions of voltage signs and the effects of inductance and capacitance on current flow, while others express uncertainty and seek further clarification on specific points.

Contextual Notes

Participants note the complexity introduced by the absence of a voltage source and the theoretical nature of charge behavior in capacitors. There is also mention of the potential for oscillation in the presence of an inductor, which adds to the discussion's depth.

mganap
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Hi guys.

Say you have a RCL circuit with a resister, capacitor, and inductor in series without a voltage source. You can write

V_R + V_C + V_L = 0

by the loop rule. But assuming everything is not zero, one of those potential differences must be the opposite sign of the other two. Which one is it? It seems to me that the inductor and resister slow down the charges while the capacitor could sort of speed them up (talking very loosely here, of course). So does it make sense to say

V_C = V_R + V_L

or is that incorrect? Also, does the addition of a sinusoidal voltage source affect the sign of anything (like the inductor, most likely)?

I'm actually a little embarrassed to be asking this question as I am a senior physics major, but I haven't worked with circuits in a long time. The sign for voltage drops in a circuit seems like a very fundamental thing to know, but I haven't seen it clearly explained anywhere I have looked.

Thanks.
 
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mganap said:
Hi guys.

Say you have a RCL circuit with a resister, capacitor, and inductor in series without a voltage source. You can write

V_R + V_C + V_L = 0

by the loop rule. But assuming everything is not zero, one of those potential differences must be the opposite sign of the other two. Which one is it? It seems to me that the inductor and resister slow down the charges while the capacitor could sort of speed them up (talking very loosely here, of course). So does it make sense to say

V_C = V_R + V_L

or is that incorrect? Also, does the addition of a sinusoidal voltage source affect the sign of anything (like the inductor, most likely)?

I'm actually a little embarrassed to be asking this question as I am a senior physics major, but I haven't worked with circuits in a long time. The sign for voltage drops in a circuit seems like a very fundamental thing to know, but I haven't seen it clearly explained anywhere I have looked.

Thanks.

Welcome to PF.

Well your confusion is natural. The convention is fairly arbitrary I think. While we intuitively think of electrons that are the things in motion - with the physical positive charges of a conductor carried by the protons of the metal material conductor, the positive convention is one that is inspired by modeling potential energy insofar as "current" flows might be thought to flow more like objects behave in a gravity field.

It goes from higher to lower, and in doing so loses (dissipates) energy through say a resistor. To do this though it makes it confusing as the "positive current" isn't electrons - its holes in the positive framework that are bubbling down as the electrons rush upwards.

That at least is my understanding of it. If there are others that would want to amplify or dissent, please feel free to pile on.

In the example you cite, the absence of a voltage source makes it more difficult for me to consider, as absent a voltage, or variance in voltage, the inductor is in theory a short and any capacitor charge would be more theoretical than anything else without further context. Any sign you would apply to it would be arbitrary, but at least for your interest should be aligned + to - whichever direction you might choose. But again that would be my understanding and how I would deal with it and perhaps others have different understanding and would feel comfortable offering up more insight than I have.

Hope that helped, and if it didn't cheers any way.
 
For DC circuitry, you would want to take into account that there will be a certain behavior of the current and voltage over time. The interesting thing you might get from this is that the behavior of the voltage and current for each of the three might be out of phase for some time and then converge to some value as time continues. For AC circuitry, the interesting thing is that there is a continuous phase constant between the three.
 
Thanks for both of your responses. You bring up some very good insights. However, my question may be a bit simpler than what you guys are talking about. Let me try to re-phrase it in a more concrete way.

Say you have a +5 voltage source in series with a resister, a capacitor and an inductor. We may write

5 - IR +/- Q/C +/- L*dI/dt = 0

My question is, what are the signs in front of the C and L terms?

What I'm really getting at is this: you can model a RLC circuit as a damped oscillator. The typical differential equation I've seen for this is

L*d^2Q/dt^2 + R*dQ/dt + Q/C = V

However, I think at least one term on the left hand side must be negative. I believe this because, as mentioned in my first post, if the voltage source is 0 we have

V_R + V_L + V_C = 0

But if the capacitor is charged a bit initially, the terms won't all be zero, so one of the terms must be the opposite sign of the other two. I also think I remember back when I worked with circuits that, when using the loop rule, resisters and capacitors have opposite signs when in series.

Does this make sense?
 
mganap said:
... if the voltage source is 0 we have

V_R + V_L + V_C = 0

But if the capacitor is charged a bit initially, the terms won't all be zero, so one of the terms must be the opposite sign of the other two.

In a static case (DC) the voltage source is just not 0 then in the case that you describe, because if you have charge over the capacitor then you have voltage and that in the fullness of time is all there is to that.

But the usefulness of RLC circuits involves the properties of the elements themselves under changing conditions. For instance when you are increasing the voltage across an inductor L the voltage increase inhibits the current increase, hence the current lags the voltage change. With a capacitor the opposite is true. The voltage lags the current because current must build up the charge in the c to create the voltage across it.

At resonance then in an RLC circuit you have balanced the complex expressions of impedance for each element to create a wholly resistive equivalent that you can express in terms of omega.

So to answer your question about the instantaneous reckoning of values across the components the best way of dealing with that is to look at the Inductance as going in the same direction (inductance resists current flow) as the resistor and treat the capacitor as acting to inhibit voltage build up or having opposite sign.
 
LowlyPion said:
So to answer your question about the instantaneous reckoning of values across the components the best way of dealing with that is to look at the Inductance as going in the same direction (inductance resists current flow) as the resistor and treat the capacitor as acting to inhibit voltage build up or having opposite sign.

This does answer my question. Thanks!

LowlyPion said:
In a static case (DC) the voltage source is just not 0 then in the case that you describe, because if you have charge over the capacitor then you have voltage and that in the fullness of time is all there is to that.

However, I'm not sure that I agree with this. If I am reading you correctly, you are saying that you need to have a voltage source in the circuit in order for the capacitor to hold charge. I don't think this is true, at least theoretically. If you charge the capacitor with a voltage source and then quickly switch the source out of the circuit, the charge on the capacitor plates will want to dissipate out. But the damping effect from the resister will require that this process is not instantaneous, so there will be some finite time when the capacitor holds a charge without a voltage source in the circuit. With the addition of the inductor as well, I think the charge will oscillate from one side of the capacitor to the other.
 
mganap said:
I don't think this is true, at least theoretically.

Theoretically many things are possible, eh?

Perhaps it's my semantics that's troubling you. My point is that once you are talking about DC, or even more extremely a short to ground and not charge and voltage changes, then the impedance components of the active elements L and C don't have a lot of meaning except as they discharge and react to some change. In that analysis you would supply signs according to current flow through the resistor. But that isn't really a 0 volt DC calculation, so much as a step function to 0 calculation - which "theoretically" speaking I don't consider as merely a DC voltage source of 0.

EDIT:
With the addition of the inductor as well, I think the charge will oscillate from one side of the capacitor to the other.

As you note there is the damping effect of the resistor. You will only see decay as there is no real drive to force charge flows to reverse. L resists but does not reverse.
 
Last edited:

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