Why have two inverters in series?

[KillaKem]

I was looking at the datasheet for the 74HCT139 and noticed that it's logic diagram consists of inverters in series, why is this? Aren't two logical inversions equivalent to no logical inversion at all?

Datasheet(pg 4) : http://lbk.fe.uni-lj.si/pdfs/PV-IC-datasheet/74HC139.pdf

 

[DragonPetter]

Not sure. One possible explanation I could give is that they provide buffering of some sort, or possibly additional timing delays.

 

[yungman]

Buffering the output. Inside the logic, you use small geometry transistors to increase the speed and shorten the prop delay. But those small transistors cannot drive the capacitance of the external circuits of the pcb traces and the loads. So they need one more buffer to drive out. Just like people put an emitter follower to beef up the drive. Usually the simplest buffer is inverting, nothing more than that.

In fact, for CMOS, they need multiple drivers one bigger than the other to build up the drive. In CMOS, the killer is the input capacitance of the gate. If you go from the high speed internal small transistors to drive a big output buffer, it will slow the circuit down so much. So the small transistor first drive a little bigger transistor which provide a better drive. Then the little bigger transistor then drive the next bigger one...so on...until the last one that can really drive. CMOS inherent is very very fast as you can see the CPU processor running in over 2GHz inside ( as you see the Intel claimed of 2.8GHz etc.) But there is no way the it can drive the external bus. The CMOS logics you see seems slow because of the buffering. That is the reason the external bus speed of those Intel processors is much much slower than the claimed internal speed.

FYI, that's the reason processors put L1 casche ( spelling) and L2 inside and can run really really fast. They don't have to drive load inside and can skip all the buffers...AND smaller too!