Engineering Why is my output current so low in this Transconductance Amplifier cell?

[arhzz]

Homework Statement

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Relevant Equations

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Hello; I am trying to build a Gm cell using a degenerated differential pair; I also have a Common Feedback Circuit so that I can keep the output at Vdd/2; This is how my Gm Cell looks like

Basically I have M1 and M2 Nmos and i feed it a differential voltage, the bottom transistors are a part of a current mirror that is being biased (and that works I have checked it) ; at the top are diode connected PMOS as loads (M3 and M4) and than I have a push pull stage; M13 is part of a enable circuit and can be disregarded. (the red things around the transitors are small signal parameters I didnt show them so its easier to see the schematic)

Now this is my test bench

I have a block that converts a single to differential voltage and feed it to the Gm; also the biasing is here done via an ideal current source and the CMFB and CMFB_ideal blocks are used to create 0.75 (so Vdd/2) at vop and von; for that purpose I also have the 2 large resistors and the 0V sources are only there so that I can measure the current; The CMFB block is working as intented since the voltages vop and von are 0.76 and my goal is to have them at 0.75

Now as you can see I am biasing it with 2.3u and I am expecting that at my Iop and Ion; but this is what I get at Iop

I get something in nA; Now I am genuinly confused why this is the case;

I plotted the currents in the 2 Transistors in my Gm2 block that are connected to IOP (M16 and M18) and this is how they look like

A little bit more than 2.3uA but still nowhere near nA; Can anyone maybe try and guide me through how I can figure out where this is going wrong?

Thanks in advance

 

[Baluncore]

Your schematic files are inserted into your post as .webp files, with insufficient resolution for me to read them reliably. Maybe attach a .png or jpg or a .pdf format file.

I have previously simulated transconductance amplifiers in LTspice.
What is your simulation software?
Can you give a link to a paper that discusses the circuit block you are using?

 

[Baluncore]

As far as I can see, all the currents in the mirrors on the pos side are equal, and all the currents on the neg side are equal. When you subtract the equal currents in the output stage, you get very close to zero.

I think you need to cross-couple the mirrors, so the currents being subtracted are reinforcing in the output. Here is a schematic with the cross-over that I think you are missing.

 

[arhzz]

Hello; just for reference here is the circuit I am building

NOTE: the bottom 2 transistors on the far left and right (The push pull stage) are susposed to be NMOS here they are PMOS but they are susposed to be NMOS and I have built them in as NMOS;

Now I have the left side of this circuit as my positive output and the right side as my negative output, and yes all the currents in the mirrors are equal I have tried playing with the W/L ratios of the mirrors and I can get to different output currents but still to no result;

For that cross couple how would I realize it in this schematic, I would like to try that

Also simulating in Xschem

Thanks!

 

[Baluncore]

For that cross couple how would I realize it in this schematic, I would like to try that

In my diagram, Iabc is the amplifier bias current, then the I+ notation should be interpreted as Iabc +I ; with I- being Iabc -I , where I± is the unbalance current that flows through the resistor between the input pair sources.

Your circuit is the same as mine, except I cross over the p-channel drains to the mirror inputs, in the middle of each side. Simply cut the vertical tracks and cross connect the sides. It will make a big difference. X and Y mark the cuts, and the connections needed.

 

[arhzz]

In my diagram, Iabc is the amplifier bias current, then the I+ notation should be interpreted as Iabc +I ; with I- being Iabc -I , where I± is the unbalance current that flows through the resistor between the input pair sources.

Your circuit is the same as mine, except I cross over the p-channel drains to the mirror inputs, in the middle of each side. Simply cut the vertical tracks and cross connect the sides. It will make a big difference. X and Y mark the cuts, and the connections needed.
View attachment 361056

Okay that helped kind of; my current i(vop) the one i have posted in #1 is still in nA but its shape resembles a lot more what I am looking for and its going from 0 to 16nA which is the behaviour I am looking for (for it to start at 0 and then rise)

I think I left something important out tho; if you look at my test bench in #1 the output of my gm cell is connected to my CMFB circuit and there is where I measure the currents that I am plotting; for some reason even tho I save the screenshot as an .png I cannot post it as .png it auto converts to .webp so I will focus on exactly what I mean for readibility

So basically I am biasing my gm cell with 2.3u; than the current IOP and ION are connected to my CMFB; here is where I setup my common mode to VDD/2; This is how the CMFB block looks like from the inside;

I am giving it the same bias current as the gm cell and the outputs VO_P and VO_N are connected to my gm cell;

Now I am certain that this is influencing the current I get out of Gm and probably what is making it be so low but I do not really understand how I need to setup the current in here with W/L of the NMOS and PMOS so that it does not make my current go in nA

Any insights?

Thanks

PS: If the resulution is still not sufficient, u can downlad the picture with right click save as and open it and zoom in.

 

[Baluncore]

Any insights?

Check to see that the OTA works as expected, without your cmfb, which may be zeroing your outputs. I connected resistors to the output, to convert the output current to a voltage relative to a reference voltage.

An OTA has a bidirectional current output. The voltage at the output will be determined by the circuit load. If you want a voltage out, connect the output to a resistor. If you want to integrate a signal, connect the output to a capacitor.

You need to specify the application for the OTA.

 

[arhzz]

Check to see that the OTA works as expected, without your cmfb, which may be zeroing your outputs. I connected resistors to the output, to convert the output current to a voltage relative to a reference voltage.

An OTA has a bidirectional current output. The voltage at the output will be determined by the circuit load. If you want a voltage out, connect the output to a resistor. If you want to integrate a signal, connect the output to a capacitor.

You need to specify the application for the OTA.

Okay I kind of did that. If you look at the circuit I posted in #4, I first built and tested the differential pair with the diode connected PMOS loads, without the Push Pull stage. I loaded the circuit such that Rload matched my Gm,where Gm is 1/Rs and the circuit works as intended (if you would like I can post the circuit and the simulation results).

I also tried simply adding the push pull stage and simulating but it didnt work, so i needed a CMFB circuit.

So the circuit worked fine without the push pull stage, when I added that it "broke" the circuit

 

[Baluncore]

I first built and tested the differential pair with the diode connected PMOS loads, without the Push Pull stage.

You need to test it with an Rload on the P-P stage, as that is the first place that has Iabc current subtraction to near zero.

 

[arhzz]

So remove the CMFB and just place loads on the Gm2 as it is (with P-P stage)?

I did that; in the following way; so this is how the circuit looks like now

What I changed are the value for the load I made them to match Gm = 1/Rs and I also made the transistor values in my Gm cell such that M18 carried 2.3u current and M16 carried 1.15u current.

With this setup I get the perfect output; everything is as I expect it (and want).

Now I went a step further and added back the CMFB circuit; basically I want to test 2 things;

1. Will the CMFB keep my Vop and Von at VCM = Vdd/2 even without the 100Meg (where Meg is Mega) resistors since that is what is keeping my current so low;

2. What kind of current ratio (or better said W/L) ratio do I need in the transistors M16 and M18 to get the wanted output and why;

So first I left the 500k Rload and put M18 and M16 W and L both 1u tested it and this is what I get;

I get around 0.77V which is I think acceptable, even without the 100Meg resistors. So I think it is safe to say that I do not need large resistor to keep my common mode "afloat". The only reason why I had them in the first place is because I tried doing this without the CMFB circuit. I tried by simply putting 2 very large resistors at the output and connecting VCM to it.

Now for the second part; I want to figure out what currents I need in my M16 and M18, and in my CMFB to get the wanted output; for starters I left all of the transistors in CMFB W=L=1um and focused on the Gm cell
Without the CMFB it showed that I needed 2.3u current in M18 and the half of that in M16 to get the wanted output; So I did that and got that M18 should have W = 2u and M16 should have W = 0.74u and these are the currents I get;

Now I checked my output and its not quite what I want, its an improvement but not there yet;

As you can see I hit 2.3uA which is what I want but it doesnt start from 0 and doesnt go to 0; hence my iout is not correct and gm is a bit to low (I am expecting 3uS)

Now I would like to figure this out why this is happening, mostly why do I need the transistor setup in my gm cell to be like that, where one transistor carries 2.3u and the other one half of the current. Any other setup where both transistor have 1.15u or 2.3u leads to the same problem I had at the beginning with the nA current.

Excuse the long post,looking forward to your feedback!

Many thanks!

 

[Baluncore]

Hello; just for reference here is the circuit I am building

I am having to guess too much here.
A web address for the circuit you show, is written across the top of the picture, and then partly cropped. What site, or text, is that circuit from?

Since it has confused some N-channel and P-channel MOSFETs, and forgotten to cross-connect the mirrors, it may have other problems.

If your Gm circuit does not work when first tested, it is important that you get it right, before inventing a CMFB circuit to fix a misunderstanding, or a typo in the documentation. Get back to first principles, specify the application, and what the circuit is required to do. Keep well away from the CMFB circuit while debugging the Gm module.

Things, such as the length and width of channels, should remain stable during testing. There are too many ways of contaminating a model by trial and error, before it can be made to work as expected. Finding and correcting earlier changes, can be more difficult than going back to the fundamentals, and starting again.

Edit. It appears we posted at the same time.

 

[Baluncore]

You have only one positive supply, Vs and ground, yet you connect load resistors between ground and the current outputs. That is asymmetric. You need to reference the load to Vs/2, or you are testing only current sourcing, never sinking at the output. That may explain the failure to reach zero.

You could use two equal load resistors, one to the positive rail, the other to ground. Or you could define two supplies, symmetrical, with ground as the reference.

There is a possible problem with having too low a supply voltage for the MOSFET Vgs. You then have far-from-ideal current mirrors, such that Vsd is controlling the circuit.

 

[arhzz]

I will talk to my professor about this; but to answer at least one of your question; that link that is cropped off is just where I should download the docker that contains Xschem, has nothing to do with the actual task

I will get back to you after I ask my professor.

Thanks!

 

[arhzz]

Sorry it took me so long to get back to this, but I have solved my issue. The answer was a diffrential resistor at the output (Iop and Ion) such that it matches my degeneration resistor. The current without the degeneration resistor is exactly what I expect it (Ibias) and with the degenration resistor it is lower for an amount that I can calculate with a formula I got from my professor.

Thank you for your help!