Recent content by Jony130

Yes, I notice this. And I reupload the corrected file.

Crossover distortion are the cause of this spikes. Too low output stage quiescent current. Try this circuit:

Try read this page https://www.dos4ever.com/flyback/flyback.html#flyback2

If for simplicity we assumed that the first stage output is -In(x) and the second stage gain is 2 and the last stage gain is e(x) we have y = e^( -In(x)*2 ) = 1/(x^2). Of course, the first and the last stage are not ideal they add offset (Is*R) but this is normal.

The long time ago I drew this diagram. And it fits to the description given by Baluncore.

I think that you should start to use "black box" approach. Don't go too deep into the subject. In the first circuit, we have one voltage source and one resistor. This one resistor is connected directly across the voltage source terminals ( two terminals A and B). From point B to A the voltage is...

Voltage is measured as the difference in potential between two points. A voltmeter has two leads which must be connected to the two points whose potential difference is to be measured. Any two points may be chosen. One of this point is treated as a reference point. We have a very similarity...

It's all depend on what do you want to achieve. For exampel you can build a simply boost converter just using a 555 timer and some transistor. http://www.dos4ever.com/flyback/flyback.html#boost2

If Vout drops the voltage at Verror will rise, this means that as long as Verror > Vramp the voltage at Vswitch is high so the duty cycle increase.

Change NMOS name into M1 . Upper M1 is a transistor designation number not the sim MODEL.

DC to DC converters behaves just like a ideal "DC" transformer. And for the boost converter n = Vout/Vin = 1/(1 - D) but this is true only when the inductor is working in continuous conduction mode (CCM), the inductor current never reaches 0A. And all component are ideal also Vin is kept...

As pointed out by Baluncore we never use this type of circuit without some sort of a negative feedback to "set" DC conditions. No, your model is just fine. I for Rd = 5k and Rs = 3.25k get Id≈400μA in LTspice You can also use this model .model n VDMOS (Vto=0.7 Kp=3.2m)

I don't understand, could you please explain what you mean? But maybe this will help http://booksite.elsevier.com/samplechapters/9780750679701/9780750679701.PDF (page 22 Understanding the Inductor) Yes, this rise is due to magnetic flux build up. This rise "stops" if we saturate the core...

Vce(sat) is a voltage difference between Vbe - Vbc. And in saturation region both of this junction (b-e and b-c ) conduct the current. http://ecee.colorado.edu/~bart/book/book/chapter5/ch5_3.htm#5_3_4 And do not forget about "silicon resistance" and "leads" resistance.

Maybe this will help you. Let us see how the AC input current flow in CE amplifier supply from a single supply. First we bias the BJT in the "linear region" via RB, RE resistors and 5V voltage source to be able to amplifier any AC voltage. Vc = 6V (red plot ); Ve = 2V (green plot) ...