74138- 3 to 8 decoder hex address help

[his_tonyness]

Homework Statement

4. FIGURE 1 shows how a 3 to 8 line decoder (74138) can be used in conjunction with NAND gate (74133) to connect a set of switches to the data bus of a microprocessor system via buffers (74367). Answer the following questions relating to the diagram:

a) What address, in HEX, is required on the address bus in order to read the switches?

b) RD and MEMRQ are control lines from the CPU. What must their logic state be in order to read the switches?

Figure 1

Homework Equations

The Attempt at a Solution

1.(a) I think the address is A3

(b) They both have to be low in order to read the switches.

I have very little knowledge regarding how these components work so would like confirmation or a point out in the right direction please.

 

[lewando]

These datasheets should help with extending your knowledge:
http://www.ti.com/lit/ds/symlink/sn74s133.pdf
http://www.ti.com/lit/ds/symlink/sn74ls138.pdf
http://www.ti.com/lit/ds/symlink/sn74365a.pdf

Your answer for a) does not look right. What were your thoughts on this?
Your answer for b) looks right.

 

[his_tonyness]

Thanks for your reply

For (a) I am not entirely sure how to interpret the hex address of the "address bits" i.e A₀, A₁₅ etc. I think if I understand correctly it is to do with memory maps. It could be something really simple but I don't understand the circuit diagram well enough.

 

[lewando]

For state of the Input switches to appear on the the Data bus, signals /RD and /MEMREQ have to be in the correct state (which you correctly established). In addition, each address bit needs to be in a specific state (high or low). Break the job into parts:
0. Understand how the '138 works
1. What does it look like address bits A₁₅..A₄ are doing?
2. How about A₃?
3. A₂..A₀?

 

[his_tonyness]

The 138 works as a 3 to 8 bit decoder where 3 inputs can deliver (2³) 8 outputs

For a NAND gate if MEMRQ is low the A₁₅ to A₄ have to be high.

A₃ is part of the data enable along with RD and the NAND output.

A₀ to A₂ are address lines, part of the ABC logic table where all inputs except one are high

A₀ to A₂ select the the lower address of the '138. The other address (A₁₅ to A₄) are used to select the memory location or the upper address. Don't know where hex address comes into it. At first I was just converting the outputs of the truth table into hex.

 

[lewando]

For a NAND gate if MEMRQ is low the A15 to A4 have to be high.

Right. You have determined 12 bits out of the 16 bit address.

A3 is part of the data enable along with RD and the NAND output.

Okay, so what should its state be to enable the '138?

A0 to A2 are address lines, part of the ABC logic table where all inputs except one are high

What output of the '138 are you interested in? What then should A₂..A₀ be?

Don't know where hex address comes into it.

Once you establish the state of all the address bits, you can represent that as a 16-bit binary value. This binary pattern can then be represented a a hexadecimal value.

 

[his_tonyness]

Ok thanks this is the gap knowledge I needed to fill here goes;

The data output 0 of the '138 is connected to the buffers, so according to the truth table we need ABC to be low in order to connect to the buffers.

A₃ needs to be high to establish the data enable.

So the 16 bit binary I have is 1111 1111 1110 1000 which in Hex is FFE8

 

[lewando]

The data output 0 of the '138 is connected to the buffers, so according to the truth table we need ABC to be low in order to connect to the buffers.

Right.

A3 needs to be high to establish the data enable.

Right.

So the 16 bit binary I have is 1111 1111 1110 1000 which in Hex is FFE8

Not right. You correctly said A₁₅..A₄ needed to be all high. You are this close.

 

[his_tonyness]

Close indeed! 1111 1111 1111 1000 or FFF8

 

[lewando]

!

 

[his_tonyness]

Thanks for your help, you have filled a valuable gap in my knowledge too!

 

[Michael Neo]

I would welcome clarification of some aspects of this question.

(1) How was it determined that: “For a NAND gate if MEMRQ is low the A15 to A4 have to be high.”?

(2) Does the NAND gate apply to A15 to A4? It is only connected to A5 and A11.

I know MEMRQ is an "Active low", i.e. it is 0 when it is active.
Therefore, since it is active in order to read the switches, the logic state is 0.

Any advice would be greatly appreceated!

 

[lewando]

(1) How was it determined that: “For a NAND gate if MEMRQ is low the A15 to A4 have to be high.”?

I think I have to apologize for the informal usage of the language. The statement:

"For a NAND gate if MEMRQ is low the A15 to A4 have to be high"

would be improved if it were worded:

"If you want to read the state of the switches, then one of the things that needs to happen is to enable the output of the '138. To do that (using the nand gate shown), then MEMRQ needs to be low and address signals A15 to A4 need to be high".

(2) Does the NAND gate apply to A15 to A4? It is only connected to A5 and A11.

The figure is not an exact schematic. it is a stylized schematic used to make a sketch of the circuit idea. I read it as "A15 to A4", otherwise why use the huge NAND gate? [EDIT: the real reason it can be assumed that the notation reads "A15 to A4" is that it is a good use of memory to map one address to one thing--in this case, one input port representing the state of the switches. If only address bits A15 and A4 (you said "A5 and A11"-- I assume a typo) were driving the NAND gate, then address bits A14 to A5 could be in any state-- resulting in a large number of addresses (I leave it to you to think about what that large number would be) that could be mapped to the input port]

I know MEMRQ is an "Active low", i.e. it is 0 when it is active.
Therefore, since it is active in order to read the switches, the logic state is 0.

This is true.

By the way, the "enabling" part of the '138, as shown, is even a little goofy. The 3 unlabled (2 unconnected) pins are assumed to be connected in a way that allows a single-signal enable via the output of the NAND gate. Many unspoken assumptions. I can understand your need for clarification. [EDIT: I am the one who may be goofy. The figure does not label the pins G1, /G2A, or /G2B causing need for clarification]

 

[Michael Neo]

Thank you for your excellent reply. I was very apprehensive about this question.
The only relevant information in the notes is the conversion of binary to hexadecimal. There isn’t an example question to practice on. There isn’t even a similar diagram. Nada.

There is a statement at the start of the module that additional reading is required. However, the reading list is empty.

NAND Gate
The NAND gate needs to output 1 to enable the 3-8-line decoder.

For the NAND gate to output 1, the inputs must be 0 and 1.

I understand why the input from MEMRQ is 0;
but, why is the input from the Address bus 1?

I’m assuming all the address bits (A₄ to A₁₅) have to be 1 for the input into the NAND gate to be 1, but why?

The Buffer
Why is the buffer important in the context of this question?

The Truth Table
A₀, A₁, A₂ contain addresses to A, B, C in the truth table.
We want to know the values of A, B, C because they will give us the address bits for A₀, A₁, A₂.

The truth table contains inputs and associated outputs. (The truth table isn't labelled with Input and Output.)
If you know one, you can determine the other.
A, B, C are input values.

However, we don’t have input values, but we can calculate the output value.
Then, we can compare this output value with the associated input values in the truth table to identify the relevant input values, i.e. A, B, C.

There is only one active output (at position 0). The other outputs are inactive.
The output is “low active”, i.e. when active its logic state is 0 and when inactive its logic state is 1.
Therefore, since there is only one active output, the output value is 0111 1111.
Then, we can compare this output value with the associated input values in the truth table to identify the relevant input values.

In this case, the input values A, B, C are 0, 0, 0.
A, B, C are addresses linked to A₀, A₁, A₂.
Therefore, A₀, A₁, A₂ are 0, 0, 0.

Binary Address
Which is the correct address and why is it the correct address?

From A₀ to A₁₅ it is: 0001 1111 1111 1111
From A₁₅ to A₀ it is: 1111 1111 1111 1000

I suspect the latter format is the correct address because the way address locations have been quoted.

This is an interesting question to attempt without relevant notes.

 

[lewando]

NAND Gate
The NAND gate needs to output 1 to enable the 3-8-line decoder.

For the NAND gate to output 1, the inputs must be 0 and 1.

No. It has been indicated by the "bubble" on the input of the '138 enable (again, poorly represented, but just go with the idea that a 0 will enable the '138 outputs) that the NAND gate needs to output 0 to enable the '138. Study the "bubble" notation.

For the NAND gate to output a 0 all 13 of the inputs need to be 1s.

I understand why the input from MEMRQ is 0;
but, why is the input from the Address bus 1?

I’m assuming all the address bits (A4 to A15) have to be 1 for the input into the NAND gate to be 1, but why?

As stated, all the inputs of the '133 need to be 1's for the output to be 0. Study the truth table in the '133 datasheet .

The Buffer
Why is the buffer important in the context of this question?

When the buffer is enabled (by the unique address), the state of the input switches is asserted onto the data bus. When you want to place other things onto the data bus, you must disable this buffer.

The Truth Table
A0, A1, A2 contain addresses to A, B, C in the truth table.
We want to know the values of A, B, C because they will give us the address bits for A0, A1, A2.

This is somewhat circular (or at least unclear to me). [A0..A2] are inputs to the '138. These are established first. Then you can follow the truth table.

The truth table contains inputs and associated outputs. (The truth table isn't labelled with Input and Output.)

Yes, but the left side is conventionally the input. Right side-- output.

However, we don’t have input values, but we can calculate the output value.

You need input values to determine the output values. If you know what the output values need to be you can figure out what the input values can be (in a gate or combinational circuit).

Then, we can compare this output value with the associated input values in the truth table to identify the relevant input values, i.e. A, B, C.

You certainly can work backwards and ask: for a given output value, what can the input values be? Which is what you are doing next:

There is only one active output (at position 0). The other outputs are inactive.
The output is “low active”, i.e. when active its logic state is 0 and when inactive its logic state is 1.
Therefore, since there is only one active output, the output value is 0111 1111.
Then, we can compare this output value with the associated input values in the truth table to identify the relevant input values.

In this case, the input values A, B, C are 0, 0, 0.
A, B, C are addresses linked to A0, A1, A2.
Therefore, A0, A1, A2 are 0, 0, 0.

Yes.

Binary Address
Which is the correct address and why is it the correct address?

From A0 to A15 it is: 0001 1111 1111 1111
From A15 to A0 it is: 1111 1111 1111 1000

I suspect the latter format is the correct address because the way address locations have been quoted.

Either one is fine as long as you associate the bit pattern with some kind of address notation. For example:

"1111 1111 1111 1000"

is ambiguous.

[A15..A0] = [1111 1111 1111 1000]

Is pretty definite.

 

[Michael Neo]

Thank you for your excellent advice and patience.

Enabling the '138

The NAND gate needs to output 0 to enable the '138.

For the NAND gate to output 0, both inputs need to be 1 and 1.

The NAND gate inputs are from (a) the Memory bus, and (b) the MEMRQ.

(a) the Memory bus - It inputs 1. OK.

(b) the MEMRQ needs to input 1.

MEMRQ is “low active”, therefore, when active its logic state is 0.
I am assuming the MEMRQ is active to read the switches; therefore, its logic state is 0.

However, if the NAND gate inputs are 1 and 0, this would produces 1.
But we want the output to be 0.

The NOT gate
HOWEVER, the MEMRQ output is connected to a NOT gate.

The NOT gate INVERTS, so, the 0 is inverted to 1.

Therefore, the NAND gate inputs are 1 and 1; therefore, the output is 0.

So, the '138 is enabled.

‘Data enable’ on the 3-8-line decoder

The data sheet is not easy to interpret – the question diagram and the data sheet diagram do not use the same terminology.

In the question, on ‘Data enable’ there is A₃ and an unlabelled part connected to the NAND gate.

Whereas in the data sheet, on ‘[Data] enable’ there is G1 and G2.

I am assuming this is different terminology for the same things. But which is which!

From the position of each in the diagrams, I suspect G1 = A₃ while G2 = NAND output.

In the above diagram, on the truth table, is the relevant line the one where A, B, C corresponds with L L L?

Thank you.

 

[Michael Neo]

For the NAND gate to output a 0 all 13 of the inputs need to be 1s.

Ah.

The NAND gate has 13 rather than 2 inputs.

They (the 13 inputs) must ALL be 1 for the NAND gate to output 0.

I thought a NAND gate only had 2 inputs.

I was looking at NAND truth tables and the physical representation of the NAND gate (2 inputs 1 output) and assumed there were only 2 inputs.

I'd assumed the Address bus input was only 1 input (0 or 1) and could only be 1 if A₁₅ to A₄ were ALL 1 (there was nothing to back this up and I wanted an explanation).

12 inputs from A15 to A4, and
1 input from the MEMRQ.

13 individual inputs makes sense.

 

[lewando]

Sounds like you are able to make things fall into place-- good work by you!

‘Data enable’ on the 3-8-line decoder

The data sheet is not easy to interpret – the question diagram and the data sheet diagram do not use the same terminology.

[EDIT-- How would you map G1, /G2A, and /G2B to /RD, A3, and the output of the NAND gate to make it work?]

From the position of each in the diagrams, I suspect G1 = A3 while G2 = NAND output.

Not so much the position, better to follow the "bubbles".

Some additional notes:
1. The bracket associated with the text "Data enable" is grouping three pins, not two, as you might have been thinking.
2. Always trust the datasheet over any schematic or representational figure.
3. The three enable inputs, G1, /G2A, and /G2B are not specified because they are not considered significant relative to intent of the figure. VCC and ground are omitted, for example. [Or not enough space in the figure to label the pins properly]. I read the figure to mean: if the output of the NAND gate is 0, [EDIT: and /RD is 0, and A3 = 1] then the '138 is enabled.

In the above diagram, on the truth table, is the relevant line the one where A, B, C corresponds with L L L?

Yes!

 

[Michael Neo]

You are an excellent and motivating tutor.

Thank you!