Bipolar totem-pole mosfet driver

[jrive]

In a lot of the literature out there, they make reference to the totem pole topology for driving Mosfets (as in an H-bridge) as shown in the figure attached. I for the life of me cannot understand how this is a good circuit. When the output from the PWM controller is high, the upper transistor is an emitter follower, so I expect to see Vout-vbe at the gate of the FET (assume no Rg for the sake of argument) -fine. However, when the PWM output is low, the upper transistor is off, but so is the bottom transistor (except perhaps while the charge stored in the FET's gate capacitance serves to provide the vbe for the bottom pnp transistor to turn on, briefly. After the cap discharges, though, the common node at the emitter of the two bipolar transistors is floating (isn't it?)...this is not a good thing, in my opinion. I would expect the high impedance input of the fet would then be susceptible to noise.

Can someone enlighten me please on what I'm missing with this topology?

Thanks!
Jorge

 

[Averagesupernova]

They are BOTH emitter followers. The bottom transistor turns on just as much as the top does at the appropriate time. It is a matter of perspective.

 

[Baluncore]

When OUT is high the upper transistor is on, conducts and pulls gate up.
When OUT is low the lower transistor is on, conducts and pulls gate down.
Vdrv is a power supply.
This is a bipolar emitter follower. It is a high current buffer capable of driving the high capacitance of the MOSFET gate.
Buffer and gate current is limited by Rgate which also prevents ultrasonic gate oscillation.

 

[jrive]

In a lot of the literature out there, they make reference to the totem pole topology for driving Mosfets (as in an H-bridge) as shown in the figure attached. I for the life of me cannot understand how this is a good circuit. When the output from the PWM controller is high, the upper transistor is an emitter follower, so I expect to see Vout-vbe at the gate of the FET (assume no Rg for the sake of argument) -fine. However, when the PWM output is low, the upper transistor is off, but so is the bottom transistor (except perhaps while the charge stored in the FET's gate capacitance serves to provide the vbe for the bottom pnp transistor to turn on, briefly. After the cap discharges, though, the common node at the emitter of the two bipolar transistors is floating (isn't it?)...this is not a good thing, in my opinion. I would expect the high impedance input of the fet would then be susceptible to noise.

Can someone enlighten me please on what I'm missing with this topology?

Thanks!
Jorge

Is it that this topology assumes the drive (the pwm output) goes above and below ground?

 

[jrive]

When OUT is high the upper transistor is on, conducts and pulls gate up.
When OUT is low the lower transistor is on, conducts and pulls gate down.
Vdrv is a power supply.
This is a bipolar emitter follower. It is a high current buffer capable of driving the high capacitance of the MOSFET gate.
Buffer and gate current is limited by Rgate which also prevents ultrasonic gate oscillation.

How does a low turn on the lower bjt? where is the current flowing from? the base is 0, and the emitter is floating (the upper transistor is off, and there is no current path (except from the gate capacitance of the MOSFET and leakage currents). In the best case, the Rgate you mention (which is huge) connects the emitter of the lower transistor to ground, and the base is also ground (when the input is low), there is no vbe,

 

[jrive]

They are BOTH emitter followers. The bottom transistor turns on just as much as the top does at the appropriate time. It is a matter of perspective.

I respectfully disagree with this statement. When the PWM output goes low, there is no vbe drop across the lower bjt. The only current path during this time is the discharge of the gate capacitance of the FET...what happens after it discharges? Isn't the FET gate floating at this time until the PWM output goes high again?
I don't see how the bottom transistor turns on just as much as the top one does. This is only true if the PWM output goes below gnd for a "low".

 

[Baluncore]

(except from the gate capacitance of the MOSFET and leakage currents)

You have answered your own question. The MOSFET gate has capacitance to both the source and drain.
The BJTs only conduct current while the gate is being charged or discharged.
MOSFET gate threshold is probably between 2 and 4 volts, so V_BE of the BJTs is not really important.

 

[jrive]

Yep, thanks @Baluncore. My concern was about the lack of voltage on the gate after that time. During the ON time of the top bjt, the gate of the FET has a steady voltage ( PWM -vbe (of the top BJT). During the ON time of the bottom BJT, the FET does not have a steady voltage driving the gate --it floats.
However, as I came to realize this morning in the shower (I do my best thinking in there, by the way, ;-)) it can only float to one VBE drop above gnd, so there is no danger of the FET inadvertently turning on during this time. The bottom BJT clamps the gate to one VBE drop above gnd so there is no problem.

Thank you @Baluncore and @Averagesupernova.