Bizarre Behavior in Discrete PMOS

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Discussion Overview

The discussion revolves around the observed behavior of the i_D vs V_ds/V_sd curves for the CD4007 MOSFET IC, specifically focusing on the unexpected delay in the PMOS curve compared to the NMOS curve. Participants explore the underlying reasons for this behavior, touching on concepts related to transistor operation, mobility of charge carriers, and measurement techniques.

Discussion Character

  • Exploratory
  • Technical explanation
  • Debate/contested
  • Mathematical reasoning

Main Points Raised

  • One participant notes that the PMOS curve appears delayed by a few volts compared to the NMOS curve and seeks explanations for this observation.
  • Another participant explains that the difference in behavior may be attributed to the higher mobility of electrons compared to holes, leading to differing slopes in the curves.
  • A third participant recalls that in CMOS circuits, PMOS transistors are typically sized larger than NMOS transistors to achieve symmetry.
  • One participant expresses confusion regarding the Id vs Vsd curve remaining zero until a certain threshold, questioning why this behavior occurs when compared to Id vs Vsg.
  • Concerns are raised about the comparison of plots due to differing axes (I(mA) for PMOS vs Vr(mV) for NMOS), suggesting that sufficient Vgs is necessary to prevent simultaneous conduction in both types of transistors.
  • A participant clarifies that a small resistor was used in series with the NMOS drain during measurements, which affects the interpretation of the current readings.
  • Another participant speculates that the zero current behavior in the Id vs Vsd curve might suggest the presence of a diode in the circuit path.

Areas of Agreement / Disagreement

Participants express differing views on the reasons behind the PMOS curve's behavior, with some attributing it to charge carrier mobility while others focus on measurement techniques and circuit configuration. The discussion remains unresolved with multiple competing perspectives present.

Contextual Notes

Participants mention potential limitations in the comparison of plots due to different measurement setups and the implications of using a resistor in the NMOS measurement. There is also uncertainty regarding the interpretation of the zero current behavior in the Id vs Vsd curve.

Apogee
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Some of my colleagues and I captured the i_D vs V_ds/V_sd curves for the CD4007 MOSFET IC (http://www.ti.com/lit/ds/symlink/cd4007ub.pdf). We did this for the NMOS and PMOS transistors. I have attached the curves to this post. The NMOS curve is as expected. However, the PMOS curve seems to be delayed by a few volts. Does anyone happen to know why the PMOS curve would have such a delay?

NMOS curve: https://raw.githubusercontent.com/Roman-Parise/Circuits-Lab/master/Spring2017/Lab2/data/nmos.png

PMOS curve: https://raw.githubusercontent.com/Roman-Parise/Circuits-Lab/master/Spring2017/Lab2/data/pmos.png
 
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The NMOS transistor operation is based on the mobility of Electrons in the Source-Drain channel.
The PMOS transistor operation is based on the mobility of Holes in the Source-Drain channel.

The mobility of Electrons is much higher than that of Holes. That translates to higher conductivity as shown in the differing slopes of the graphs you supplied.
If you want to get into the details, look at the formulae on pg 202, and the graph on pg 203 (PDF pgs 8, 9) in:
https://people.eecs.berkeley.edu/~hu/Chenming-Hu_ch6.pdf

Hope it helps.
Tom
 
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As I recall in CMOS circuits to achieve symmetry the PMOS FET has to be twice the size of the NMOS.
 
I understand these concepts, but I'm more concerned with the fact that the Id vs Vsd curve remains zero until a certain point. For Id vs Vsg, this makes sense, since there's a threshold voltage. But this doesn't make sense to me for Id vs Vsd.
 
For PMOS you show I(mA) against Vsd.
For the NMOS you show Vr(mv) vagainst Vds.
How can we compare different plots?

It may be that since devices are operated with their P and N gates tied, there needs to be sufficient Vgs to prevent heavy conduction by both P and N at the same time.
 
Baluncore said:
For PMOS you show I(mA) against Vsd.
For the NMOS you show Vr(mv) vagainst Vds.
How can we compare different plots?

It may be that since devices are operated with their P and N gates tied, there needs to be sufficient Vgs to prevent heavy conduction by both P and N at the same time.

I apologize for the confusion. A small resistor was placed in series with drain (about 100 οhms) when measuring the NMOSs drain current. Vr is the voltage drop over that resistor. So id is essentially proportional to that curve.
 
Apogee said:
A small resistor was placed in series with drain (about 100 οhms) when measuring the NMOSs drain current. Vr is the voltage drop over that resistor. So id is essentially proportional to that curve.

Might not be related to your question but that means the current range for the NMOS FET was roughly 0 to 0.9mA and for the PMOS it was 0 to 350mA?
 
Apogee said:
I'm more concerned with the fact that the Id vs Vsd curve remains zero until a certain point.

Almost as if there is a diode in the path somewhere.