Calculating UART DLL and DLM contents from Baud Rate and Clock Frequency

  • Context: Comp Sci 
  • Thread starter Thread starter Stu80
  • Start date Start date
  • Tags Tags
    Clock Frequency Rate
Click For Summary

Discussion Overview

The discussion revolves around calculating the contents of the Divisor Latch Low (DLL) and Divisor Latch High (DLM) registers for a UART based on a given baud rate and clock frequency. It includes aspects of practical application and reference to technical documentation.

Discussion Character

  • Technical explanation
  • Practical application

Main Points Raised

  • One participant states the formula for baud rate and expresses confusion about converting the calculated value of N into the HEX contents of DLL and DLM, given their maximum values.
  • Another participant shares their practical experience with similar calculations and suggests looking for built-in dividers or shifts in related standards, although they did not reference the datasheet.
  • A third participant points to specific sections of the datasheet that describe how the divisor is stored in a 16-bit format and encourages reading the entire document for better understanding.
  • The original poster acknowledges the guidance and clarifies their misunderstanding regarding the interpretation of the latches, indicating that their question has been resolved.

Areas of Agreement / Disagreement

Participants generally agree on the importance of the datasheet for understanding the divisor latches, but there is no explicit consensus on the method for calculating the HEX values for DLL and DLM from the baud rate and clock frequency.

Contextual Notes

The discussion highlights a misunderstanding regarding the representation of the divisor in the UART, specifically the interpretation of the two 8-bit latches as separate rather than part of a single 16-bit value.

Who May Find This Useful

Individuals working with UART configurations, those interested in practical applications of baud rate calculations, and readers seeking to understand UART initialization processes may find this discussion relevant.

Stu80
Messages
8
Reaction score
3
Homework Statement
A PC16550D UART has a clock running at18.432 MHz and its
baud rate is set to 2000. Determine the HEX contents of its DLM and
DLL registers
Relevant Equations
Baud rate = Clock frequency/(16×N)
I understand that,

Baud Rate = Clock Frequency / (16 x N)

and that N = DLL + DLM

when I substitute the figures to get an answer for N to be 576, how do I then convert this into the HEX contents of DLL and DLM, especially considering the maximum value for DLL or DLM is 255?

I have uploaded the PC16550D datasheet for reference if needed.
 

Attachments

Physics news on Phys.org
Fun problem, and very practical. I do this sort of thing all the time at my work.

I didn't look at the datasheet, but look for a built-in divider or shift by a couple of bits. For example, in the USB standard, the requested Icc by a device being plugged in is a factor of 2 higher (in mA) than the hex value that is reported (requested current = 2x the configuration value), and the USB host knows that.
 
Last edited:
See paragraph 8.5.1 on pg. 17 of the datasheet, and immediately following, the last two columns of Table 1.

A clue is this sentence in paragraph 8.5.1:
Two 8-bit latches store the divisor in a 16-bit binary format.
These Divisor Latches must be loaded during initialization ...

There is more information a few pages later.

In fact, I recommend you read the whole datasheet, even the confusing parts. You will remember a few of the ideas the next time you use this or similar devices, and will gradually be able to put together a mental picture of their general operational approaches.

Cheers,
Tom
 
  • Like
Likes   Reactions: berkeman and Stu80
Thank you Tom, I had already read that specific paragraph but it hadn't clicked regarding the 16-bit divisor - I was wrongly reading them as 2 separate 8-bit latches.

Question answered!

Cheers
 
  • Like
Likes   Reactions: Tom.G and berkeman