Capacitor on ground connection of Comparator input
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The discussion centers on the role of capacitors C1, C2, and C3 in a comparator circuit, with C3 identified as a low-pass filter that inadvertently removes DC reference from the inputs. The circuit is criticized for lacking credibility, as it fails to provide a return path for input bias current, raising concerns about its functionality. It is suggested that the circuit may be an academic example intended for phase shifting signals, particularly for square waves, but its practical application remains unclear. The conversation highlights the importance of understanding the original design intent and the implications of bias current and common mode voltage in circuit performance. Overall, the circuit's design appears flawed, necessitating further clarification on its intended use.
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Svein
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Actually, as it stands C3 creates a circuit error, since it removes any DC reference to the comparator inputs. Apart from that error, R1C2 and R2C1 are low-pass filters with different time constants.
Baluncore
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The circuit has little credibility as it is. Where does it come from and what was it supposed to do?
As Svein writes, the amplifier input bias voltage is blocked by C3. But the effect will be determined by the internal input structure of CMP1, an unspecified device. The two different low-pass filters suggest it may be intended to detect if input voltage is rising or falling, for a limited band of frequencies, rejecting high frequency noise in the process. Maybe it is supposed to condition a digital data stream with a known data rate or bandwidth. It is expected to always have an input signal. It is a differentiator of some form, why?
As Svein writes, the amplifier input bias voltage is blocked by C3. But the effect will be determined by the internal input structure of CMP1, an unspecified device. The two different low-pass filters suggest it may be intended to detect if input voltage is rising or falling, for a limited band of frequencies, rejecting high frequency noise in the process. Maybe it is supposed to condition a digital data stream with a known data rate or bandwidth. It is expected to always have an input signal. It is a differentiator of some form, why?
alan123hk
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Tracey3 said:capacitor C3 acts as a low pass filter
Why C3 acts as a low pass filter ?
Impedance of capacitor is 1/(jwC), higher impedance when the frequency is lowered, so it should block low frequency.
It looks more like a DC isolator in the input
R1-C2 and R2-C1 are low-pass filters, or RC delay circuits with different delay times.
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jim hardy
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Tracey3 said:I don't quite understand the purpose of C1 and C2 as indicated on the picture.
One possibility as to what somebody had in mind
and a nice Trig refresher
apply sinewave input to Vin, just say Vin = sin(1000t)
and calculate
what is voltage at V+?
What is voltage at v-?
What is the difference between them?
Draw a graph and add Vout.
Then try it at frequency 10% different.but that circuit is a terrible implementation ,
it allows no return path for "input bias current". so probably won't work.
old jim
berkeman
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Excellent point Jim! I totally missed that.jim hardy said:it allows no return path for "input bias current". so probably won't work.
Baluncore
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Once the necessary DC input bias is assumed, this circuit will provide a 90° phase shift for sine or square wave signal in the region of 1 or 2 kHz. A simple high-pass filter and amplifier will quadrature shift only a clean sine wave, but this circuit works well with square waves or trapezoidal data.
We assumed this was a real implementation of a circuit, but now it appears to be an academic example of the quadrature phase shift technique. DC bias is not relevant to signal analysis, but is critically important for the implementation of a real circuit.
Circuits similar to this were used half a century ago in modems for digital data. The reason the DC bias is not shown for this relic, might be that it was originally built using dual triodes, then later with differential pairs of PNP transistors, then NPN, now replaced symbolically by the comparator.
How it works; C3 couples AC input signals into the circuit. For in-band signals; R2⋅C1 generates a DC reference voltage that slowly follows input variations and so removes low frequency input noise and DC bias drift. R1⋅C2 is faster, so it follows the mid-band input with about 90° phase shift. The comparator output is therefore an amplified difference signal that for a sinewave is high while Vin is rising, low while Vin is falling. Without a signal it will produce noise, which is why I would expect it to have a regular input signal. HF noise on the input is reduced by R1⋅C2, which also removes harmonics, so allows it to generate a digital quadrature phase shift of square wave signals near 1 or 2 kHz.
We assumed this was a real implementation of a circuit, but now it appears to be an academic example of the quadrature phase shift technique. DC bias is not relevant to signal analysis, but is critically important for the implementation of a real circuit.
Circuits similar to this were used half a century ago in modems for digital data. The reason the DC bias is not shown for this relic, might be that it was originally built using dual triodes, then later with differential pairs of PNP transistors, then NPN, now replaced symbolically by the comparator.
How it works; C3 couples AC input signals into the circuit. For in-band signals; R2⋅C1 generates a DC reference voltage that slowly follows input variations and so removes low frequency input noise and DC bias drift. R1⋅C2 is faster, so it follows the mid-band input with about 90° phase shift. The comparator output is therefore an amplified difference signal that for a sinewave is high while Vin is rising, low while Vin is falling. Without a signal it will produce noise, which is why I would expect it to have a regular input signal. HF noise on the input is reduced by R1⋅C2, which also removes harmonics, so allows it to generate a digital quadrature phase shift of square wave signals near 1 or 2 kHz.
davenn
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It isn't ...if you had read the following posts you would have seen that Tracy3's error was correctedalan123hk said:Why C3 acts as a low pass filter ?
read the posts
jim hardy
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@Baluncore
Interesting explanation. I hadn't thought about square wave input.
I wondered if it might be some sort of Frequency to Voltage Converter for sine or triangle waves
seems it'd give an output pulse string having duty cycle that varies with frequency , over the frequency range between the two filters' 90° phase points.
Maybe a PLL building block ?
Interesting explanation. I hadn't thought about square wave input.
I wondered if it might be some sort of Frequency to Voltage Converter for sine or triangle waves
seems it'd give an output pulse string having duty cycle that varies with frequency , over the frequency range between the two filters' 90° phase points.
Maybe a PLL building block ?
Baluncore
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My logic goes like this.jim hardy said:Maybe a PLL building block ?
1. Output comparison of the same signal through two different LP filters, reduces the circuit to producing a phase shifted square wave output.
2. Input noise will become a problem for both higher or lower frequencies, due to signal attenuation, or the comparison of two similar signals. It must therefore be an application limited to mid-band.
3. It would need more circuitry before it became a PLL phase detector, a PSK or an NRZ data decoder.
The only space I see remaining for such a circuit is to extract a quadrature clock from a square or trapezoidal input stream.
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jim hardy
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How i envy you who are fluent with these simulation programs !
It looks to me like your two plots have different input frequencies and output duty cycles...?
top has input period of ~0.66 msec and output duty about 50%
and bottom has period ~0.60 msec and duty cycle ~38% ?
So the output's DC content changed , but as a result of frequency or waveshaps?
What would a DC meter on output show ?
old jim
...
It looks to me like your two plots have different input frequencies and output duty cycles...?
top has input period of ~0.66 msec and output duty about 50%
and bottom has period ~0.60 msec and duty cycle ~38% ?
So the output's DC content changed , but as a result of frequency or waveshaps?
What would a DC meter on output show ?
old jim
...
Baluncore
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Massive congratulations to PF management. The graphic files have remained very small and crisp. A vast improvement over the old process.
The Vin script for square waves is based on time, for sinewave on frequency. I did not worry about precision frequency as it generates only a slightly different phase shift of the output. It showed quadrature shift over the range between 1kHz and 2 kHz so I kept my test signal in that range.
It would also be good to know what input waveform was expected, over what frequency range. We still have no idea of the original intended application.
This simulation shows what I expected from the circuit. Given a long enough run it will produce a square wave. That is predicted because the majority of the higher harmonics are attenuated by the LPF structure. Maybe we could look for an input wave form and frequency that make this circuit a frequency doubler or tripler. That would be a situation with high sensitivity to component values.
Meanwhile it works as a reliable quadrature clock extractor.
This simulation runs for 100msec but I only show the last 2 msec. The DC levels are still settling down to a steady state. Changes in duty cycle are much greater due to variation of the DC level than they are due to input frequency.jim hardy said:So the output's DC content changed , but as a result of frequency or waveshaps?
The Vin script for square waves is based on time, for sinewave on frequency. I did not worry about precision frequency as it generates only a slightly different phase shift of the output. It showed quadrature shift over the range between 1kHz and 2 kHz so I kept my test signal in that range.
A low-pass filter on the output, with a DC meter, would show mainly duty cycle variations while C3 charged and settled down. I could write a more complex script that set the capacitor initial charge voltage, but first we would need to better define the DC bias.jim hardy said:What would a DC meter on output show ?
It would also be good to know what input waveform was expected, over what frequency range. We still have no idea of the original intended application.
This simulation shows what I expected from the circuit. Given a long enough run it will produce a square wave. That is predicted because the majority of the higher harmonics are attenuated by the LPF structure. Maybe we could look for an input wave form and frequency that make this circuit a frequency doubler or tripler. That would be a situation with high sensitivity to component values.
Meanwhile it works as a reliable quadrature clock extractor.
analogdesign
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berkeman said:Excellent point Jim! I totally missed that.
If it is a CMOS comparator the input bias current will be low enough that it can probably be supplied by the ESD diodes on the input pads. I don't think the input bias current will be a problem here.
berkeman
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Interesting thought, I'd never considered that before. I'll have to check some typical datasheets. Do you think that will still be true at -40C? Do you know approximately what the reverse leakage current is over temperature for typical protection diodes inside opamps? And the top and bottom clamp diodes are probably not typically matched very well, I would think. I'll have to think about how they could combine to provide a center-bias voltage. (Maybe there is a patent in there for you somewhere...)analogdesign said:If it is a CMOS comparator the input bias current will be low enough that it can probably be supplied by the ESD diodes on the input pads. I don't think the input bias current will be a problem here.
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jim hardy
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analogdesign said:I don't think the input bias current will be a problem here.
I'm old enough to still think in terms of LM193 type comparators, or an op-amp based one.
Thanks !
Baluncore
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The fundamental problem here is that @Tracey3 never returned to identify the origin or application of the circuit.
The suggestion that CMOS does not require bias because internal ESD protection diodes will probably fix it, is mischievous. It always amazes me what some amateurs can get away with once. But this is an engineering forum. @analogdesign, please identify a CMOS R2R comparator manufacturer that advocates employing input static protection diodes as circuit bias elements on their products.
https://e2e.ti.com/blogs_/archives/.../03/14/op-amps-used-as-comparators-is-it-okay
Bias is never a problem with a partial schematic. Bias requirements must be resolved by the engineer who implements the circuit. That engineer will take into account the technology employed for that particular implementation.analogdesign said:If it is a CMOS comparator the input bias current will be low enough that it can probably be supplied by the ESD diodes on the input pads. I don't think the input bias current will be a problem here.
The suggestion that CMOS does not require bias because internal ESD protection diodes will probably fix it, is mischievous. It always amazes me what some amateurs can get away with once. But this is an engineering forum. @analogdesign, please identify a CMOS R2R comparator manufacturer that advocates employing input static protection diodes as circuit bias elements on their products.
Let's not give the impression that op-amps can be used as voltage comparators. Op-amps are designed to operate with very low input differential voltages, so many have input voltage clamping diodes to prevent saturation, while voltage comparators are usually specified to operate with differential input voltages equal to the supply voltage.jim hardy said:I'm old enough to still think in terms of LM193 type comparators, or an op-amp based one.
https://e2e.ti.com/blogs_/archives/.../03/14/op-amps-used-as-comparators-is-it-okay
jim hardy
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Great link there, @Baluncore
Svein
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The problem is not bias current, it is about the common mode voltage range. If the "ground reference" is lost, the common mode voltage has a tendency to drift due to spurious leakage currents. Thus the comparator will suddenly stop working (believe me, I know. I once got an "alarm" call and had to travel by plane to another town only to discover that an electrician had disconnected the analog ground reference for some reason and forgotten to reconnect it).analogdesign said:If it is a CMOS comparator the input bias current will be low enough that it can probably be supplied by the ESD diodes on the input pads. I don't think the input bias current will be a problem here.
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