# Need a voltage divider for a capacitor source voltage

• imsmooth
In summary: The 1k11 resistor is used to approximate 1k11111. In the simulation, the phase error is within femto-degrees and the phase plot is a mess due to floating point resolution.
Baluncore said:
Please identify the datasheets that make those statements, that you claim to be fact.

Baluncore said:
An XOR is digital, a Gilbert cell is analogue, Gilbert cells work well at VHF frequencies.
The output does not respond to VHF only HF. The input may be VHF.

The phase detector response of the XOR gate does not follow your logic.
Baluncore said:
Voltage comparators introduce hysteresis.
How can an XOR logic gate be linear, z = a*(1-b)+b*(1-a) ?I
p7 shows DC to 50 MHz in this family . Many are more and less https://www.ti.com/lit/gpn/sn74hcs86

The way XOR gates and Gilbert multipliers alike work as linear phase detectors is to produce a pulsewidth in quadrature phase-lock proportional to the linear phase difference. The advantage of Gilbert cells only occurs from increase dynamic range for linear amplitude multiplier output not linear phase, but thus shows better results for RF analog demodulators, not used here.

The old Motorola multiplier IC has a known self-resonant frequency at 10MHz that must be avoided on the output.

TonyStewart said:
The phase detector response of the XOR gate does not follow your logic.
Can you be more specific, which logic does it not follow?

Baluncore said:
Which logic is that?
Baluncore said:
Voltage comparators introduce hysteresis.
How can an XOR logic gate be linear, z = a*(1-b)+b*(1-a) ?
See f(A) XOR f(B) has no hysteresis

TonyStewart said:
See f(A) XOR f(B) has no hysteresis
An XOR gate is not a voltage comparator, so obviously it needs no hysteresis.
Ignoring hysteresis, the XOR is still non-linear. z = a*(1-b)+b*(1-a).
That is why it can be used as a mixer, or as a direct-sequence modulator.

Respectfully, I have designed dozens of different PLL's in my career so I am quite familiar with all the characteristics and terminology. So to avoid further non-sequiturs, let me explain again. PLL's for tuning a tank circuit to resonance can be quite simple, with no need for a uC or a Gilbert Multiplier. The sine waves may be turned into logic levels with or without hysteresis if the benefit is to eliminate redundant transitions, which only reduces the gain of the loop in this very short transition.

Yet this is irrelevant as the operating point of "the loop" is always furthest away from the transitions to have a balanced DC voltage when integrated results in no change to the tuning of the VCO.

The integration may be done with open collector/drain charge pumps an active integrator, or simply the quasi-integration of a low pass filter on the error signals with sufficient loop gain.

We do not call it a direct-sequence modulator for this task. It is a frequency mixer and after integration or low pass filtering, the result is a phase detector as phase is the integral of frequency regardless of linear or digital amplitude.

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TonyStewart said:
Respectfully, I have designed dozens of different PLL's in my career so I am quite familiar with all the characteristics and terminology.
Then you need to learn that, when you are holding a hammer, everything is not a nail.

TonyStewart said:
So to avoid further non-sequiturs, let me explain again.
TonyStewart said:
We do not call it a direct-sequence modulator for this task.
Of course, we do not. I was NOT discussing PLLs, I was discussing non-linear XOR gates, as used for phase detection, or the simplest modulation application. You seem determined to misinterpret what I write, so you can then smother it in irrelevancy.

The OP wanted a wideband attenuator, without phase shift, to feed a comparator. I have simply pointed out that a multiplier, used as a phase detector, could eliminate the need for the comparator.

The OP has been careful NOT to say why the comparator was needed. You now insist that I must be wrong, because to complete what is clearly an unspecified project, you would use a digital PLL.

You are polluting the thread with amplitude "non-linear" criticisms of XOR gates that are irrelevant. The case here is for "linear-phase" not linear multiplying amplitude and phase, which is useful to mix RF signals and may be used here, but is not mandatory. Then your phase error voltage is sinusoidal at the error frequency and not a linear triangle wave with time as with XOR logic which can be implemented much simpler as indicated previously. His end goal was to make the PLL using a uC firmware measuring tank current phase. Your criticisms of my suggestions were invalid, except for requesting reference specs which did support. This should not continue here and be a parking lot discussion.

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