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Counter from 0 to 11 then back to 0 (system verilog)

  1. Mar 30, 2012 #1
    Hi all,
    i am trying to do a counter using system verilog. The counter will count from 0 to 11 then back to 0 and start the counting again.

    Input = rdy, if rdy = 0, start counting.
    Output = count

    I have done the simulation for my code and it is not working as i prefer. It will continues count until it's overflow but not back to 0 if the count = 12.
    It seems like " else if (i==12)" doesnt work. How can i fix the problem? or i should not use else if here?

    Thanks for the help
    Ivan

    Code (Text):

    always_ff @ (posedge clk,negedge rst)
      if(!rst)
          begin
          count<=0;
          i<=0;
          end
          else
            begin
            if (!rdy)
              begin
              count<=count+1;
              i<=i+1;
              end
              else if (i==12)
                begin
                  count<=0;
                  i<=0;
                end
            else
              begin
              count<=count;
              i<=i;
              end
            end
            endmodule  
     
     
  2. jcsd
  3. Mar 30, 2012 #2
    I dont know verilog, but the if ... else if ... control flow typically won't attempt to evaluate the second conditional "else if (i ==12)" in this case, if the first is true.

    there are a million and one ways to implement a counter in a hardware descriptive language. i would probably structure VHDL as
    Code (Text):

    if(rising_edge(clock) and not RST) then
          if(i<12) then
              i <= 1 + 1;
          else
              i <= 0;
          end if
    else if ( RST ) then
             count <= 0;
    end if
    its been a long time, so my syntax is probably all wrong.

    p.s, whats the point in the ready signal?
     
  4. Mar 30, 2012 #3


    Thanks for your reply
    what does RST mean?
     
  5. Mar 30, 2012 #4
    sorry, its reset. ive set it up to be asynchronous.
     
  6. Mar 30, 2012 #5

    ready is the input, if the ready=0 and last for 3 clock cycle, it will count from 0 to 2.
     
  7. Mar 30, 2012 #6
    sorry, 1 more question

    can i use count to the counting?not i.
    like
    if count < 12
    ...
    ..
    i have try that in my code but it doesnt work. is that becuase count is the output so i cannot use it for internal counting?
     
  8. Mar 31, 2012 #7
    again, I have zero experience with verilog, but since it compiles down to the same thing as VHDL, i would imagine the structure of what you can do is similar.

    in the code posted below, i and count are dealt with in exactly the same way. so unless you have declared them as different datatypes, theres no reason count would not work instead of i.

    if you declare a variable as an output, then make some conditional statements based on its value, you must also be able to read it as an input. VHDL requires that this variable be declared as "inout" or "buffer" (or perhaps "signal" or "variable")

    I assume that verilog has a similar restriction?
     
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