Counter from 0 to 11 then back to 0 (system verilog)

  • Thread starter hoheiho
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In summary: I have zero experience with verilog, but since it compiles down to the same thing as VHDL, i would imagine the structure of what you can do is similar.
  • #1
hoheiho
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Hi all,
i am trying to do a counter using system verilog. The counter will count from 0 to 11 then back to 0 and start the counting again.

Input = rdy, if rdy = 0, start counting.
Output = count

I have done the simulation for my code and it is not working as i prefer. It will continues count until it's overflow but not back to 0 if the count = 12.
It seems like " else if (i==12)" doesn't work. How can i fix the problem? or i should not use else if here?

Thanks for the help
Ivan

Code:
always_ff @ (posedge clk,negedge rst)
  if(!rst)
      begin
      count<=0;
      i<=0;
      end
      else 
        begin
        if (!rdy)
          begin
          count<=count+1;
          i<=i+1;
          end
          else if (i==12)
            begin
              count<=0;
              i<=0;
            end
        else
          begin
          count<=count;
          i<=i;
          end
        end
        endmodule
 
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  • #2
I don't know verilog, but the if ... else if ... control flow typically won't attempt to evaluate the second conditional "else if (i ==12)" in this case, if the first is true.

there are a million and one ways to implement a counter in a hardware descriptive language. i would probably structure VHDL as
Code:
if(rising_edge(clock) and not RST) then
      if(i<12) then
          i <= 1 + 1;
      else
          i <= 0;
      end if
else if ( RST ) then
         count <= 0;
end if

its been a long time, so my syntax is probably all wrong.

p.s, what's the point in the ready signal?
 
  • #3
earlofwessex said:
I don't know verilog, but the if ... else if ... control flow typically won't attempt to evaluate the second conditional "else if (i ==12)" in this case, if the first is true.

there are a million and one ways to implement a counter in a hardware descriptive language. i would probably structure VHDL as
Code:
if(rising_edge(clock) and not RST) then
      if(i<12) then
          i <= 1 + 1;
      else
          i <= 0;
      end if
else if ( RST ) then
         count <= 0;
end if

its been a long time, so my syntax is probably all wrong.

p.s, what's the point in the ready signal?



Thanks for your reply
what does RST mean?
 
  • #4
hoheiho said:
Thanks for your reply
what does RST mean?

sorry, its reset. I've set it up to be asynchronous.
 
  • #5
earlofwessex said:
I don't know verilog, but the if ... else if ... control flow typically won't attempt to evaluate the second conditional "else if (i ==12)" in this case, if the first is true.

there are a million and one ways to implement a counter in a hardware descriptive language. i would probably structure VHDL as
Code:
if(rising_edge(clock) and not RST) then
      if(i<12) then
          i <= 1 + 1;
      else
          i <= 0;
      end if
else if ( RST ) then
         count <= 0;
end if

its been a long time, so my syntax is probably all wrong.

p.s, what's the point in the ready signal?
ready is the input, if the ready=0 and last for 3 clock cycle, it will count from 0 to 2.
 
  • #6
earlofwessex said:
sorry, its reset. I've set it up to be asynchronous.

sorry, 1 more question

can i use count to the counting?not i.
like
if count < 12
...
..
i have try that in my code but it doesn't work. is that becuase count is the output so i cannot use it for internal counting?
 
  • #7
hoheiho said:
sorry, 1 more question

can i use count to the counting?not i.
like
if count < 12
...
..
i have try that in my code but it doesn't work. is that becuase count is the output so i cannot use it for internal counting?

again, I have zero experience with verilog, but since it compiles down to the same thing as VHDL, i would imagine the structure of what you can do is similar.

in the code posted below, i and count are dealt with in exactly the same way. so unless you have declared them as different datatypes, there's no reason count would not work instead of i.

if you declare a variable as an output, then make some conditional statements based on its value, you must also be able to read it as an input. VHDL requires that this variable be declared as "inout" or "buffer" (or perhaps "signal" or "variable")

I assume that verilog has a similar restriction?
 

FAQ: Counter from 0 to 11 then back to 0 (system verilog)

1. What is the purpose of counting from 0 to 11 then back to 0 in system verilog?

The purpose of this type of counting is to create a loop that repeats a specific sequence of actions multiple times. It is commonly used in digital circuits to control the timing and sequence of operations.

2. How does the counter in system verilog count from 0 to 11 then back to 0?

The counter in system verilog uses a modulo operator to keep track of the count and reset it to 0 after reaching 11. This allows for a continuous loop of counting from 0 to 11 and back to 0.

3. Can the counter in system verilog count in a different sequence, such as 0 to 10 and back to 0?

Yes, the sequence of the counter can be changed by modifying the value passed to the modulo operator. For example, if the value is changed to 10, the counter will count from 0 to 10 and back to 0.

4. Is it possible to reset the counter in system verilog to a different starting value?

Yes, the counter can be reset to a different starting value by using a conditional statement to check for a specific condition and resetting the counter to the desired value if the condition is met.

5. What are some common applications of a counter in system verilog?

Counters are commonly used in digital circuits for tasks such as generating clock signals, controlling data transfer, and sequencing operations. They can also be used in testing and debugging processes.

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