- #1
hoheiho
- 47
- 0
Hi all,
i am trying to do a counter using system verilog. The counter will count from 0 to 11 then back to 0 and start the counting again.
Input = rdy, if rdy = 0, start counting.
Output = count
I have done the simulation for my code and it is not working as i prefer. It will continues count until it's overflow but not back to 0 if the count = 12.
It seems like " else if (i==12)" doesn't work. How can i fix the problem? or i should not use else if here?
Thanks for the help
Ivan
i am trying to do a counter using system verilog. The counter will count from 0 to 11 then back to 0 and start the counting again.
Input = rdy, if rdy = 0, start counting.
Output = count
I have done the simulation for my code and it is not working as i prefer. It will continues count until it's overflow but not back to 0 if the count = 12.
It seems like " else if (i==12)" doesn't work. How can i fix the problem? or i should not use else if here?
Thanks for the help
Ivan
Code:
always_ff @ (posedge clk,negedge rst)
if(!rst)
begin
count<=0;
i<=0;
end
else
begin
if (!rdy)
begin
count<=count+1;
i<=i+1;
end
else if (i==12)
begin
count<=0;
i<=0;
end
else
begin
count<=count;
i<=i;
end
end
endmodule