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[verilog] change from always@ to assign

  1. Sep 28, 2012 #1
    1. The problem statement, all variables and given/known data
    Halo, I have written a always@ (code i,pic1) which can output what I want but the result is delayed 1 clock cycle, therefore I have changed it to assign (code ii,pic2)and try to output the recover signal immediately when pcreg_1 is changed. But waveform is not what I wanted. Did I miss somethings in (code ii)? The recover is high in 2 clock cycle and I cannot get 0.

    code i
    Code (Text):
    always @(posedge clk)
    begin
      if (store)
          if (m2==pcreg_1)
            recover = 0;
          else
            recover = 1;
      else
          if (m1==pcreg_1)
            recover = 0;
          else
            recover = 1;    
    end
    code ii
    Code (Text):
    assign recover = (store && (m2==pcreg_1))? 1'b0:1'b1;
    assign recover = (!store && (m1==pcreg_1))? 1'b0:1'b1;
    Could anyone give me a hand for me :(?

    Thank you very much for help
    Ivan
     

    Attached Files:

  2. jcsd
  3. Oct 1, 2012 #2
    Did anyone can see whats the problem :(?
     
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