Decoding DDR Memory Organization: Understanding 1Gb DDR2 SDRAM Datasheet

  • Thread starter Thread starter likephysics
  • Start date Start date
  • Tags Tags
    Memory
Click For Summary
SUMMARY

The discussion focuses on the organization of 1Gb DDR2 SDRAM, specifically its structure of rows, columns, and banks. The 1Gb capacity is derived from 64Mb*16 data lines, which translates to 8Mb*8 banks with 16 data lines. The datasheet indicates 13 row address lines (2^13 = 8192) and 8 column address lines (2^8 = 256), leading to a total organization of 8192 rows by 256 columns by 64 bits per bank. Additionally, the necessity of precharging a row before selection is raised, highlighting the operational requirements of DDR memory.

PREREQUISITES
  • Understanding of DDR2 SDRAM architecture
  • Familiarity with memory addressing concepts
  • Knowledge of binary calculations (e.g., powers of two)
  • Basic comprehension of memory precharging mechanisms
NEXT STEPS
  • Research DDR2 SDRAM timing parameters and their impact on performance
  • Learn about memory bank organization and its effects on access speed
  • Study the precharge operation in DDR memory and its significance
  • Explore the differences between DDR2 and DDR3 SDRAM architectures
USEFUL FOR

Electronics engineers, memory design specialists, and students studying computer architecture will benefit from this discussion on DDR2 SDRAM organization and operational principles.

likephysics
Messages
638
Reaction score
4
I was going through the datasheet of 1Gb DDR2 SDRAM. It's organized in rows, columns and banks.
The 1Gb is actually 64Mb*16 datalines.
Which is 8Mb*8 Banks * 16 data lines
I can't figure out how they got 8Mb?

In the datasheet block diagram (attached), there are 13 row address lines. So 2^13 = 8k
there are 8 column addr lines, so 2^8 = 256
8192*256 = 2Mb ?
 

Attachments

  • 64MBx16.png
    64MBx16.png
    44.7 KB · Views: 632
Engineering news on Phys.org
Hi likephysics. Each bank is actually organized as 8192 by 256 by 64 bits. There are 10 column select bits, but only 8 of them are used to actually select the column. The remaining 2 are used to select the correct 16 bit word from the 64 bit bank output.
 
uart, Thanks.
One more DDR question - why do you need to precharge a row before selecting it?
 

Similar threads

  • · Replies 1 ·
Replies
1
Views
2K
  • · Replies 4 ·
Replies
4
Views
7K
Replies
12
Views
9K