Design a synchronous circuit using negative edge-triggered D

[trickae]

Homework Statement

(Problem 225) Design a synchronous circuit using negative edge-triggered D
flip- flops that provides an output signal Z which has one-fifth the frequency of the clock
signal. Draw a timing diagram to indicate the exact relationship between the clock
signal and the output signal Z. To ensure illegal state recovery, force all unused or
illegal states to go to 0. [Hint: There are many answers to this problem.]

Homework Equations

The Attempt at a Solution

would like tips on how to even begin an attempt

 

[berkeman]

Show us your timing diagram for this divide-by-5 synchronous circuit.