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Design a synchronous circuit using negative edge-triggered D

  1. Apr 21, 2007 #1
    1. The problem statement, all variables and given/known data
    (Problem 225) Design a synchronous circuit using negative edge-triggered D
    flip- flops that provides an output signal Z which has one-fifth the frequency of the clock
    signal. Draw a timing diagram to indicate the exact relationship between the clock
    signal and the output signal Z. To ensure illegal state recovery, force all unused or
    illegal states to go to 0. [Hint: There are many answers to this problem.]


    2. Relevant equations



    3. The attempt at a solution

    would like tips on how to even begin an attempt
     
    Last edited: Apr 21, 2007
  2. jcsd
  3. Apr 25, 2007 #2

    berkeman

    User Avatar

    Staff: Mentor

    Show us your timing diagram for this divide-by-5 synchronous circuit.
     
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