(Problem 205) Design a synchronous counter that has a Moore output decimal
sequence of 0, 1, 3, 5, 7, and then repeats this same sequence over and over. To
ensure illegal state recovery, force all unused or illegal states to go to 0. Carry out
the design using positive edge-triggered T flip-flops. Draw the circuit diagram.
The Attempt at a Solution
I have no idea how to begin to attempt the solution any tips would be highly appreciated
currently reading wakerly chapter 7 to cover the basis of the problem