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Design a synchronous counter that has a Moore output decimal

  1. Apr 21, 2007 #1
    1. The problem statement, all variables and given/known data
    (Problem 205) Design a synchronous counter that has a Moore output decimal
    sequence of 0, 1, 3, 5, 7, and then repeats this same sequence over and over. To
    ensure illegal state recovery, force all unused or illegal states to go to 0. Carry out
    the design using positive edge-triggered T flip-flops. Draw the circuit diagram.


    2. Relevant equations



    3. The attempt at a solution

    I have no idea how to begin to attempt the solution any tips would be highly appreciated
    currently reading wakerly chapter 7 to cover the basis of the problem
     
    Last edited: Apr 21, 2007
  2. jcsd
  3. Apr 25, 2007 #2

    berkeman

    User Avatar

    Staff: Mentor

    What does a Moore machine look like. Show us your state transition diagram, and we can help if you still are confused.
     
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