[Digital Systems]NAND-Gate Implementation

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Discussion Overview

The discussion revolves around the implementation of a digital circuit using NAND gates to achieve the output function Z=A'C+BC', where A, B, and C are inputs. Participants explore methods for constructing the circuit, including the use of DeMorgan's theorem and the role of K-Maps in simplification.

Discussion Character

  • Homework-related
  • Technical explanation
  • Mathematical reasoning
  • Exploratory

Main Points Raised

  • One participant expresses uncertainty about how to start the problem and requests hints for implementation.
  • Another participant suggests that K-Maps are unnecessary for this simple expression and emphasizes the cost-effectiveness of using only NAND gates for circuit construction.
  • A participant explains how NOT, OR, and AND gates can be constructed using NAND gates and provides a tutorial link for further guidance.
  • One participant applies DeMorgan's theorem to derive an alternative expression for Z and questions whether their approach is valid.
  • Another participant shares a logic diagram to illustrate their method of assembling NAND gates and canceling redundant gates.
  • Several participants discuss the cancellation of redundant gates, specifically the removal of inverters, and clarify that two inverters effectively cancel each other out.
  • A participant introduces a new topic by asking about the differences between registers and flip-flops, indicating a shift in focus within the discussion.

Areas of Agreement / Disagreement

Participants generally agree on the feasibility of implementing the function using NAND gates and the validity of using DeMorgan's theorem. However, there is some confusion regarding the removal of inverters and the implications of that step. The discussion on registers and flip-flops introduces a new area of inquiry, indicating that multiple topics are being explored without a clear consensus on all points.

Contextual Notes

Some participants express uncertainty about the initial steps for the problem, and there are unresolved questions about the implications of removing certain components in the circuit design. The discussion also touches on different methods of circuit assembly and simplification, which may depend on individual interpretations of the problem.

Who May Find This Useful

Students studying digital systems, particularly those interested in circuit design using NAND gates, as well as individuals seeking clarification on concepts related to registers and flip-flops.

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Homework Statement


For the output function Z=A'C+BC'

Where A,B,C are inputs and A',B',C' are the complements of the inputs respectively

Implement the design using only NAND GATES


Homework Equations


K-Map, maybe?


The Attempt at a Solution


I haven't taken digital system design course in years, so I don't even know where to start this problem. Can somebody start me off with some hints then I'll attempt the problem?
 
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this one is pretty simple. You don't need to worry about K-Maps because K-Maps are for simplifying messy boolean expressions. The expression you have, Z=A'C+BC' is a very simple one.

In practice, constructing a digital circuit is cheapest by implementing it using only NAND gates, so I guess the idea is to show you how it's done.

Basically each component, NOT, OR, AND, can each be made up of an assortment of NAND gates. All you do is put little blocks of these NAND gate configurations together the same as you would with regular NOT, OR, and AND gates.

Here's a good quick tutorial on it:
www.colchsfc.ac.uk/electronics/pdf_files/Doing it All With NAND Gates and NOR Gates.pdfHope this helps.
 
verd said:
this one is pretty simple. You don't need to worry about K-Maps because K-Maps are for simplifying messy boolean expressions. The expression you have, Z=A'C+BC' is a very simple one.

In practice, constructing a digital circuit is cheapest by implementing it using only NAND gates, so I guess the idea is to show you how it's done.

Basically each component, NOT, OR, AND, can each be made up of an assortment of NAND gates. All you do is put little blocks of these NAND gate configurations together the same as you would with regular NOT, OR, and AND gates.

Here's a good quick tutorial on it:
www.colchsfc.ac.uk/electronics/pdf_files/Doing it All With NAND Gates and NOR Gates.pdf


Hope this helps.

(Hits head) Of course, Demorgan's!

Ok so basically

Z = A'C+BC'

Setting A'C = X, BC' = Y

Z = X + Y
Z' = (X'Y')'
Z' = [(A'C)'(BC')']'

Since DeMorgan's theorem gives Z', for Z, just make an inverter at the end to complement the function. Is this a valid solution?
 
You can use NAND gates to make up all of the other gates. The way I look at it is like blocks, I just put them together and cancel redundant gates when everything is assembled.

I made the following to illustrate what I'm trying to say:
http://img36.picoodle.com/img/img36/9/9/3/f_logicdiagram_f42f88a.jpg


Hope this helps
 
why u remove implements in last step?
 
awais bashir said:
why u remove implements in last step?

two inverters cancel out each other.
in other words, if you have a's complement's complement, that's just a itself!
 
what are registers& and flip floop..and difference b/w them.?
 

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