Implement a function with 2-input NAND gates

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Discussion Overview

The discussion revolves around implementing a logical function using only 2-input NAND gates. Participants are exploring the conversion of a given function expressed in Sum of Products (SOP) and Product of Sums (POS) forms into a circuit design constrained to NAND gates. The conversation includes aspects of Karnaugh Maps (K-Maps) and the construction of logic gates from NAND gates.

Discussion Character

  • Technical explanation
  • Mathematical reasoning
  • Debate/contested

Main Points Raised

  • One participant presents a function derived from a K-map and seeks assistance in implementing it using only 2-input NAND gates.
  • Another participant asks for clarification on the K-map results and inquires about constructing an OR gate from NAND gates.
  • A participant mentions they know how to create an OR gate for two variables but is unsure about extending it to more variables.
  • There is a suggestion to build a wider OR gate using a tree structure of 2-input OR gates, but the original poster emphasizes the restriction to NAND gates.
  • A later reply points out the need to include inverters in each OR stage, highlighting a potential oversight in the circuit design.
  • Participants reiterate the constraint of using only 2-input NAND gates, which is a rule from the exercise.

Areas of Agreement / Disagreement

Participants generally agree on the need to use only 2-input NAND gates, but there is disagreement on how to effectively implement the required logic function under this constraint. The discussion remains unresolved regarding the specific implementation steps.

Contextual Notes

Participants have not fully resolved how to construct multi-input OR gates using only NAND gates, and there are missing details on the specific implementation of the function based on the K-map results.

alfonwob
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Hello people!

I've just done a K-Map and gotten both the SOP and POS, but have a problem with this function:

f = acd + cab + dab + cdab + abcd ,
f = (a+b+c+d) * (b+c+d) * (b+c+d) * (a+b) * (a+c) * (a+d)

and got to implement it only using NAND gates with 2 inputs. Notice the underline is the negated variable.

Thank you so much in advance.
 
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alfonwob said:
Hello people!

I've just done a K-Map and gotten both the SOP and POS, but have a problem with this function:

f = acd + cab + dab + cdab + abcd ,
f = (a+b+c+d) * (b+c+d) * (b+c+d) * (a+b) * (a+c) * (a+d)

and got to implement it only using NAND gates with 2 inputs. Notice the underline is the negated variable.

Thank you so much in advance.

Welcome to the PF.

What did you get from your K-map? Do you know how to make an OR gate from NAND gates to implement your SOP solution?
 
Hi, thanks for your answer. I got (1 / 1 / 0 / 0 ... 0 / 1 / 0 / 0 ... 1 / 0 / 1 / 0 ... 0 / 1 / 0 / 0 ) I know how yo do an OR gate from 2 variables, not for more.

Image last number in right bottom is 0, not 1.
 

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alfonwob said:
Hi, thanks for your answer. I got (1 / 1 / 0 / 0 ... 0 / 1 / 0 / 0 ... 1 / 0 / 1 / 0 ... 0 / 1 / 0 / 0 ) I know how yo do an OR gate from 2 variables, not for more.

Image last number in right bottom is 0, not 1.

To build a wider OR gate, you just make a tree of 2-input OR gates...

http://www.electronics-tutorials.ws/logic/log11.gif
log11.gif
 
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berkeman said:
To build a wider OR gate, you just make a tree of 2-input OR gates...

http://www.electronics-tutorials.ws/logic/log11.gif
log11.gif

Thanks again for helping me.
Ok I understand the image you've attached but I have just to use NAND gates with 2 inputs.

I upload a picture where I show you the step I'm stuck in, just in the the part when I have to add both terms.
 

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You need to include the inverters as part of each OR stage. You show the final stage without those inversions...
 
But I only have NAND gates with 2 inputs. It's a rule from the exercise.
 
alfonwob said:
But I only have NAND gates with 2 inputs. It's a rule from the exercise.

You already show in that drawing how to use a 2-input NAND to make a NOT gate... That's how you got your first 2 NOR gate equivalents...
 

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