Implement a function with 2-input NAND gates

[alfonwob]

Hello people!

I've just done a K-Map and gotten both the SOP and POS, but have a problem with this function:

f = acd + cab + dab + cdab + abcd ,
f = (a+b+c+d) * (b+c+d) * (b+c+d) * (a+b) * (a+c) * (a+d)

and got to implement it only using NAND gates with 2 inputs. Notice the underline is the negated variable.

Thank you so much in advance.

 

[berkeman]

Hello people!

I've just done a K-Map and gotten both the SOP and POS, but have a problem with this function:

f = acd + cab + dab + cdab + abcd ,
f = (a+b+c+d) * (b+c+d) * (b+c+d) * (a+b) * (a+c) * (a+d)

and got to implement it only using NAND gates with 2 inputs. Notice the underline is the negated variable.

Thank you so much in advance.

Welcome to the PF.

What did you get from your K-map? Do you know how to make an OR gate from NAND gates to implement your SOP solution?

 

[alfonwob]

Hi, thanks for your answer. I got (1 / 1 / 0 / 0 ... 0 / 1 / 0 / 0 ... 1 / 0 / 1 / 0 ... 0 / 1 / 0 / 0 ) I know how yo do an OR gate from 2 variables, not for more.

Image last number in right bottom is 0, not 1.

 

[berkeman]

Hi, thanks for your answer. I got (1 / 1 / 0 / 0 ... 0 / 1 / 0 / 0 ... 1 / 0 / 1 / 0 ... 0 / 1 / 0 / 0 ) I know how yo do an OR gate from 2 variables, not for more.

Image last number in right bottom is 0, not 1.

To build a wider OR gate, you just make a tree of 2-input OR gates...

http://www.electronics-tutorials.ws/logic/log11.gif

 

[alfonwob]

To build a wider OR gate, you just make a tree of 2-input OR gates...

http://www.electronics-tutorials.ws/logic/log11.gif

Thanks again for helping me.
Ok I understand the image you've attached but I have just to use NAND gates with 2 inputs.

I upload a picture where I show you the step I'm stuck in, just in the the part when I have to add both terms.

 

[berkeman]

You need to include the inverters as part of each OR stage. You show the final stage without those inversions...

 

[alfonwob]

But I only have NAND gates with 2 inputs. It's a rule from the exercise.

 

[berkeman]

But I only have NAND gates with 2 inputs. It's a rule from the exercise.

You already show in that drawing how to use a 2-input NAND to make a NOT gate... That's how you got your first 2 NOR gate equivalents...