EE Circuit State Diagram Analysis and Design

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itsmyname
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Homework Statement


Before drawing and simulating the circuit, use the steps given in the text to analyze the circuit shown in the figure below. Finish with a properly formatted state diagram with the state of the JK-type flip-flop designated as Q1 and the state of the D-type flip-flop as Q0. Note that the circuit has one primary input DI and one output DO. For purposes of the analysis, ignore the direct input CLR. Also, note that the circuit uses a Moore model since the output is a function of the state variables (Q1, Q0) only.
Include your analysis, state diagram and state table.

Logic circuit schematic with a FJKC flip-flop labeled Q1 and an FDC flip-flop labeled Q0. Input DI feeds J and K of Q1, Q1's Q output feeds D of Q0, and CLK drives the clock inputs of both; CLR feeds the CLR inputs, and DO is the output of Q0.



Could someone please help with just the first couple states? I am having trouble figuring out the final output.
 

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