Extending MIPS datapath to implement SLL and SRL

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To extend the MIPS datapath for implementing SLL (shift left logical) and SRL (shift right logical), an additional multiplexer (mux) is necessary next to the register file to select between Read data 1 and Read data 2 based on the operation type. The mux should output Read data 1 when not performing a shift and Read data 2 when executing a shift operation. Furthermore, the shift amount must be extracted from Instruction[10:6] and fed into the ALU, requiring another mux to select this value when a shift operation is indicated. The instruction bits will also need to be routed through a sign extender before being processed by the ALU when ALUSrc is set to 1. This approach outlines the necessary modifications for implementing the desired shift operations in the MIPS architecture.
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Homework Statement


Here's the datapath:
nM8IuyM.png


So this seems like a pretty common question but I can't seem to find any answers on how to extend the datapath to implement SLL and SRL.

The Attempt at a Solution



This is how I would think to do it but I'm not entirely sure:

It would need another mux right next to Read data 1 next to the register file. This mux would take Read data 1 (rs) and Read data 2 (rt) as inputs. It would select Read data 1 if we're not doing a shift operation, and it would select rt if we ARE doing a shift operation (since sll and srl use rt, not rs). This would then be fed into the ALU.

Next, we would need to branch Instruction[10:6] (the shift amount) off of Instruction[15:0], and Instruction[10:6] would then be fed into the other port of the ALU. Is this correct thinking?
 
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It looks like I'd actually need to feed Instruction[10:6] and Instruction[15:0] into another Mux and have it select Instruction[10:6] when I want to shift, which will then be sent through the sign extender and into the ALU when ALUSrc is set to 1. Right? Anyone?
 

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