1. Jan 18, 2013

### Wallboy

I'm currently learning the MIPS architecture and am implementing my own version of the ISA in a logic simulator. I'm sure I understand the differences between Byte and Word addressing, but I don't understand why we need Byte Addressing.

How I currently have my memory system implemented, is I have a 32x32 sized RAM. When I address my memory, I leave the lower two bits disconnected from the address input so all my addresses end in 00, or a value divisible by 4. This way all the addresses between a a number divisible 4 select the same data. Example of the PC addressing some instruction:

Code (Text):

0x00000000        0x1234ABCD              0x00000000
0x00000001        0x1234ABCD              0x00000000
0x00000002        0x1234ABCD              0x00000000
0x00000003        0x1234ABCD              0x00000000
0x00000004        0x567890EF              0x00000001
0x00000005        0x567890EF              0x00000001
...

Now for implementing load byte instructions, I use a 4:1 MUX where each of the inputs is 8 bits that make up each Byte of the 32 bit word of data. I then use the offset value within the load byte instructions as the select to the MUX to select which byte I want. Then sign/zero extend the value to be written back to the register file.

This is where I don't see the use of using byte addressing when we can just use word addressing and use some simple logic like the MUX to select individual bytes within the 32 bit word.

2. Jan 19, 2013

### Staff: Mentor

It seems to me that you answered your own question. If you can directly access an indivisual byte within a word, doesn't that seem more efficient (i.e., fewer instructions, therefore faster) than doing all of the stuff you described?

Although it doesn't seem to be done much any more, in times past, programmers would optimize loop bodies that executed many times by minimizing the number of instructions that had to be performed each loop iteration. Sometimes the goal was to reduce the size of the code when the amount of memory was limited, and sometimes the goal was to speed up the processing time.

If the code was redrawing the image on the screen, you would want to be able to address each byte.

3. Jan 19, 2013

### AlephZero

The hard part is not just doing byte operations, but doing them efficiently. For example, suppose you want to store several bytes from the same word in different registers, to do some fast processing, and then recombine them back into memory (and for extra credit, do the same with multiple processors!)

You won't make many friends with compiler-writers, if you design a machine like that!

FWIW the first versions of Unix on Cray supercomputers (back in the 1980s) were totally crippled because of this issue - the Cray 1 was a (64-bit) word addressible machine only, and dealinig with Unix data structures that were a mix of 8, 16, and 32 bit quantities was S---L---O---W.

4. Jan 19, 2013

### Wallboy

Well my implementation of my MIPS ISA is single cycle. Every instruction is done in one cycle. I plan on doing some multi-cycle and parallel implementations after this to compare.

So were the first implementations of Byte Addressing using an actual physical address to point to each byte between words? Unless memory back then was built as 32x8 so each address actually was a single byte. But then again I doubt this, since how would you see the entire word with a single byte address.

To me it seems there is no such thing as "physical" byte addressing and it's really just a term to describe how one should implement the addressing of the bytes and halfwords that make up a word.

But if that is the case then why add this complexity of byte addressing so we have to add shifters with our instructions that involve any sort of memory access or branch/jumping to maintain proper word alignment. Wouldn't it just be easier if it was all just word aligned: PC+1, no shifting for proper alignment, etc? All it took was a single multiplexer to extract a byte in my implementation.

5. Jan 21, 2013

### HowlerMonkey

Does it have bus/dma mastering on isa?

This is an issue with the current solutions to use isa in a newer system.

6. Jan 21, 2013

### rcgldr

yes.
This is not an issue for reads, and both the old core memories and most modern dram memories have to be "erased" by reading before writing, so a read / modify a byte / write operation on a 32 / 64 / 128 bit block of memory doesn't involve any additional overhead. Caching will help reduce overhead when writing multiple sequential bytes, since writes will then utilize the full width of the memory in this case.