# Questions about the operation of this C68MX11 CPU

• Michael Neo
In summary: Accumulator is an 8-bit register that stores intermediate results of arithmetic and logic operations. It is fed into the ALU and then CCR can store the result in the accumulator D.
Michael Neo
Homework Statement
This question refers to the C68MX11 CPU, details of which accompany this assignment.
(Data sheet: http://www.moxsyn.com/data_sheets/C68MX11_cpu.pdf)

a) With reference to the block diagram of the CPU, what is the purpose of the program stack and the accumulators A, B and D?

b) Again with reference to the block diagram, outline how the processor would add two numbers held in ACC.A and ACC.B, the result being stored in memory.

c) Give the address range in hex that the PC could access.
Relevant Equations
None.
Part (a)

The Purpose of the Accumulators

The accumulator is a register for short-term, intermediate storage of arithmetic and logic data in a CPU.

(The term "accumulator" is rarely used in reference to contemporary CPUs, having been replaced around the turn of the millennium by the term "register". In a modern computers, any register can function as an accumulator. )

With reference to the block diagram of the CPU, although the data busses have a width of 8-bits most of the instructions have 16-bit equivalent instructions.

The C68MX11 offers multiply, add, subtract, compare, increment and decrement, load & store, and shift instructions of 16-bit operands.

The CPU consists of 8-bit accumulators used to hold operands and results of arithmetic calculations or data manipulations.

The accumulator A and B can be combined into a 16-bit double accumulator D that can store these 16-bit equivalent instructions.

From the data sheet:

The Purpose of the Program Stack

From the data sheet: “The CPU automatically supports a program stack. This stack may be located anywhere in the 64 Kbyte address space through the stack pointer and may be any size up to the amount of memory available in the system.

Definition
A stack is a data structure.
A stack is a linear data structure which follows a particular order in which the operations are performed.
A stack is an array of memory dedicated to temporary storage.

Structure
A stack is, typically, a LIFO data structure.
A stack stores data from the top down.

Function
A stack pointer is a register that stores, and is used to indicate, the address of the last item put onto the stack.
• When a new data item is entered or "pushed" onto the top of a stack, the stack pointer increments to the next physical memory address, and the new item is copied to that address.
• When a data item is "pulled" from the top of a stack, the item is copied from the address of the stack pointer, and the stack pointer decrements to the next available item at the top of the stack.
Summary:
• Stack is a linear data structure.
• Typically, but not exclusively, LIFO.
• Stack Pointer is a register that indicates address of last item put on stack.
• Stack Pointer decreases when you put an item on the stack.
• Stack Pointer increases when you pull an item from the stack.

In this CPU, the stack is located anywhere in the 64 Kbyte address space via the stack pointer, and can be up to the amount of memory available in the system.

Part (b)

ACC.A and ACC.B are accumulators.

Accumulator A is the most significant octet while Accumulator B is the least significant octet.

The contents of these two 8-bit accumulators are fed into the ALU and then via the CCR are stored in Accumulator D.

Accumulators are used to store intermediate arithmetic and logic results and then fed to the next immediate level, i.e. the ALU.

OR

Add values stored in ACC.A and ACC.B and put the result in ACC.D, then run a separate cycle to store ACC.D in memory via the address bus and data port.

The binary operands are brought to the ALU via two inputs from ACC.A and ACC.B via the bus.

The 16 bit index registers IX and IY are used for indexed addressing modes.

1. Direct
2. Extended
3. Indexed
Part (c)

1 KB = 1024 Bytes
64 KB = 65536 Bytes
So, address range = 0 to 65535

0 = 0x0
65535 = 0xFFFF

0x0 to 0xFFFF

Last edited:
Michael Neo said:
Part (a)
a) With reference to the block diagram of the CPU, what is the purpose of the program stack
You have described how the stack operates, but the problem asks why there is one.
Michael Neo said:
Part (b) outline how the processor would add two numbers
The "OR in the middle of your answer(s) is problematic. Both parts are accurate. The first part defines the registers and their general usage, which is useful. But by itself is an incomplete response to the problem statement.

I agree.

Michael Neo
Part (a)

Program stacks are used to support: expression evaluation, subroutine return address storage, dynamically allocated local variable storage, and subroutine parameter passing.

Expression Evalution

To see why a program stacks is used, consider how the following arithmetic expression would be computed:
X = (A + B) * (C + D)
First, A and B would be added together.
Then, this intermediate result must be saved somewhere.
It is pushed onto the expression evaluation stack.
Next, C and D are added, and the result is also pushed onto the expression evaluation stack.
Finally, the top two stack elements (A+B and C+D) are multiplied and the result is stored in X.
The expression evaluation stack provides automatic management of intermediate results of expressions, and allows as many levels of precedence in the expression as there are available stack elements.

...

Dynamically Allocated Local Variable Storage

...

Subroutine Parameter Passing

...

Are general reasons for having a stack applicable to this CPU. Is that all that is required?
It is a relatively old CPU.

Part (b)

ACC.A and ACC.B are accumulators: accumulator A and accumulator B respectively.
Accumulator A is the most significant octet while Accumulator B is the least significant octet.
These two general-purpose 8-bit accumulators are used to store operands and results of arithmetic calculations or data manipulations and then fed to the next immediate level, i.e. the contents of these two 8-bit accumulators are fed into the 16-bit ALU.
The binary operands are brought to the 16-bit ALU via two inputs from ACC.A and ACC.B via the bus.
Then a separate cycle is run to store ACC.D (accumulator D) in memory via the address bus and data port, via the CCR, are stored in 16-bit Accumulator D.

The 16 bit index registers IX and IY are used for indexed addressing modes.
1. Direct
2. Extended
3. Indexed

This doesn't seem correct - A and B to ALU via CCR to D to CCR to memory? Or A and B (which comprise D) to ALU via CCR to memory?

Michael Neo said:
Are general reasons for having a stack applicable to this CPU.
Can't tell without a detailed description of the instruction set.
However the problem statement was:
Michael Neo said:
what is the purpose of the program stack
Michael Neo said:
This doesn't seem correct - A and B to ALU via CCR to D to CCR to memory? Or A and B (which comprise D) to ALU via CCR to memory?
Yea, it does seem a bit off.
• A and B to ALU via CCR to D
and
Then a separate cycle is run to store ACC.D (accumulator D) in memory via the address bus and data port, via the CCR, are stored in 16-bit Accumulator D. {a leftover sentence fragment here?}

I don't see where A & B go thru the CCR to get to the ALU, it seems to be a direct route; {register}-->ALU. The main purpose of CCR is to hold flag bits that reflect ALU results, so things like the Carry out of an operation can be used as input to the next ALU instruction, or to test if a Conditional Branch instruction should be taken or not.
• Or A and B (which comprise D)

This wording seems to imply that D is a way of treating the A and B registers as a single item. I reality, D is another register that is separate from A and B.

Michael Neo
This wording seems to imply that D isa way of treating the A and B registsrs as a single item. In reality, D is another register that is separate from A and B.

The confusion stems from the wording of the data sheet:

The CPU consists of two general-purpose 8-bit accumulators used to hold operands and results of arithmetic calculations or data manipulations. The accumulator A and B can be combined into a 16 bit double accumulator D.

So, this actually means the contents of A and B can be placed into D?

With reference to the block diagram of the CPU, what is the purpose of the program stack and the accumulators A, B and D?

The program stack
In the data sheet, it states:

“The CPU automatically supports a program stack. This stack may be located anywhere in the 64 Kbyte address space through the stack pointer and may be any size up to the amount of memory available in the system.”

The program stack is a data structure that operates, typically, LIFO.

A stack pointer is a register that stores, and is used to indicate, the address of the last item put onto the stack.

When a new data item is entered or “pushed” onto the top of a stack, the stack pointer increments to the next physical memory address, and the new item is copied to that address.

When a data item is “pulled” from the top of a stack, the time is copied from the address of the stack pointer, and the stack pointer decrements to the next available item at the top of the stack.

The purpose of the program stack is to store information about the active subroutines of a computer program, expression evaluation, subroutine return address storage, dynamically allocated variable storage, and subroutine parameter passing.

[This doesn't seem enough. "With reference to the block diagram of the CPU..." How can the block diagram be specifically related to the purpose of the program stack? I've described, why a program stack is needed and I've described why a stack pointer (special register) is needed to enable this.]

The accumulators A, B and D
In the data sheet, it states:

“Although the data busses have a width of 8 bit most of the instructions have 16 bit equivalent instructions. The C68MX11 offers multiply, add, subtract, compare, increment & decrement, load & store, and shift instructions of 16 bit operands. The CPU consists of two general-purpose 8-bit accumulators used to hold operands and results of arithmetic calculations or data manipulations. The accumulator A and B can be combined into a 16 bit double accumulator D.”

An accumulator is a register for short-term storage of operands, and results of arithmetic calculations or data manipulations.

Accumulator A and B are 8-bit while accumulator D is 16-bit.

However, most of the instructions have 16-bit equivalent instructions but the data busses have a width of 8-bits.

The contents of the 8-bit accumulators A and B can, after manipulation, be stored in 16-bit double accumulator D; after, for example, information from A and B is taken to the 16-bit ALU.

[Again, this doesn't seem enough. It is simply regurgitating the quote from the data sheet. With reference to the block diagram of the CPU..." How can the block diagram be specifically related to acumulators A, B and D?]

Last edited:
Part (b)

So, the CCR is not involved at all!

How is the output of the ALU directed to ACC.D?

Michael Neo said:
The confusion stems from the wording of the data sheet:
The confusion was mine. I misread the data sheet block diagram. The A and B can combine to form the D register. Sorry.
Michael Neo said:
So, the CCR is not involved at all!
Yup, it just holds the status of the most recent ALU operation.
Michael Neo said:
How is the output of the ALU directed to ACC.D?
If there are 16-bit arithmatic instructions, the ALU result must go to both A and B registers. Then 16-bit Store insructions could write the D register (A and B combined) to memory.

I can see you have read that datasheet in more detail than I have! I have less experience with the Motorola 6800 family than I do with the Intel 8080 family of CPUs... and it shows!

I think you have pretty well got it now. Hang in there.

Cheers,
Tom

Michael Neo

## 1. What is the C68MX11 CPU and how does it work?

The C68MX11 CPU is a central processing unit (CPU) that is commonly used in embedded systems. It is designed to perform various operations and execute instructions, allowing the device to function properly. It works by receiving instructions from the device's software, processing them, and then sending the results back to the software.

## 2. What are the main features of the C68MX11 CPU?

The C68MX11 CPU has a 16-bit instruction set and can operate at a clock speed of up to 20 MHz. It also has a built-in memory management unit (MMU) and supports various input/output (I/O) interfaces, making it suitable for a wide range of applications.

## 3. How does the C68MX11 CPU handle interrupts?

The C68MX11 CPU has a built-in interrupt controller that can handle both hardware and software interrupts. When an interrupt occurs, the CPU will stop its current operation, save its current state, and then execute the interrupt service routine (ISR) to handle the interrupt. Once the ISR is completed, the CPU will resume its previous operation.

## 4. Can the C68MX11 CPU be programmed in different languages?

Yes, the C68MX11 CPU can be programmed in various languages such as assembly, C, and C++. However, the programming language used will depend on the specific development environment and tools available for the device that is using the CPU.

## 5. How does the C68MX11 CPU handle memory management?

The C68MX11 CPU has a built-in MMU that is responsible for managing the device's memory. It uses a paging system to map virtual addresses to physical addresses, allowing the device to have access to a larger memory space than its physical memory capacity. The MMU also helps to protect the device's memory from unauthorized access.

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