FPGA Troubleshooting: Spartan 3E-1600 MicroBlaze Dev Board

[eemichael83]

I've recently purchased an FPGA development board from Digilent, particularly the Spartan 3E-1600 MicroBlaze development board. Back in school, we did some very basic VHDL development with Cypress WARP but ran as simulations. I wanted to expand on that and learn something that the industry uses (on something tangible), so I chose Xilinx FPGA's and Verilog HDL. Their current free development package is the ISE WebPack 13.4 which is what I'm trying to use. I've started with a very basic XOR function with two inputs and one output but it isn't working. For anyone familiar with this development package, my process has been the following:

1.Start a new project and select the 'Spartan-3E 1600E MicroBlaze Dev Board' option (the board I bought) in the Design Properties and hit Ok.
2.Then, add new 'Verilog Module' source.
3. Define the module with In0 and In1 Inputs, and Out0 Output (Direction for these set accordingly).
4. Add 'assign Out0 = In0 ^ In1;' line to the Verilog source (.v file) between module and endmodule.
5. Open PlanAhead and assign my Inputs to 'L13' and 'L14', Output to 'R14'. I also add pullup to the inputs and set output drive to 8. (verified by checking my .ucf file)
6. Run Synthesize - XST, Run Implement Design, then Run Generate Programming File (all check marks).
7. Check .bit file and it is 729KB.

I was told by Xilinx customer service that the .bit file shouldn't be this large but I cannot figure out why it is. The board I have has two PROM devices, each 4Mb so the .bit file for this simple XOR will not even fit on one PROM device. I tried programming the FPGA directly with this .bit file and got an unresponsive board and I also tried programming the PROM devices with the .bit file cascaded and programming the FPGA from the PROM, same result (no surprise there).

I would greatly appreciate any help that anyone might be able to provide me as I am stumped.

 

[berkeman]

I've recently purchased an FPGA development board from Digilent, particularly the Spartan 3E-1600 MicroBlaze development board. Back in school, we did some very basic VHDL development with Cypress WARP but ran as simulations. I wanted to expand on that and learn something that the industry uses (on something tangible), so I chose Xilinx FPGA's and Verilog HDL. Their current free development package is the ISE WebPack 13.4 which is what I'm trying to use. I've started with a very basic XOR function with two inputs and one output but it isn't working. For anyone familiar with this development package, my process has been the following:

1.Start a new project and select the 'Spartan-3E 1600E MicroBlaze Dev Board' option (the board I bought) in the Design Properties and hit Ok.
2.Then, add new 'Verilog Module' source.
3. Define the module with In0 and In1 Inputs, and Out0 Output (Direction for these set accordingly).
4. Add 'assign Out0 = In0 ^ In1;' line to the Verilog source (.v file) between module and endmodule.
5. Open PlanAhead and assign my Inputs to 'L13' and 'L14', Output to 'R14'. I also add pullup to the inputs and set output drive to 8. (verified by checking my .ucf file)
6. Run Synthesize - XST, Run Implement Design, then Run Generate Programming File (all check marks).
7. Check .bit file and it is 729KB.

I was told by Xilinx customer service that the .bit file shouldn't be this large but I cannot figure out why it is. The board I have has two PROM devices, each 4Mb so the .bit file for this simple XOR will not even fit on one PROM device. I tried programming the FPGA directly with this .bit file and got an unresponsive board and I also tried programming the PROM devices with the .bit file cascaded and programming the FPGA from the PROM, same result (no surprise there).

I would greatly appreciate any help that anyone might be able to provide me as I am stumped.

Do you see the Xilinx device in the JTAG chain correctly before you try to program anything? Do you have any sample programs or examples that came with the Development Board that you can try directly?

 

[eemichael83]

Do you see the Xilinx device in the JTAG chain correctly before you try to program anything? Do you have any sample programs or examples that came with the Development Board that you can try directly?

Yes, I see the FPGA, both PROM's, and the CPLD on the board in the JTAG chain. The service rep told me that the reason my file is unresponsive on the FPGA is likely due to whatever reason my .bit file is so large, but I can't figure out why that is. The process is pretty straight forward so it's hard for me to imagine what I've done wrong.

BTW, no sample programs came with the board and I wasn't able to find any on their site either. It did ship with a 'test' program pre-programmed that counted up in base 10 on the LCD and counted up in binary on the LED's. This pre-programmed sample worked correctly on the board but I have no source for it.

 

[eemichael83]

In the most recent email to Xilinx (different service rep, the initial rep only responded to the first email and nothing further), they gave this response:

"A .bit file is actually always the same size dependent upon the board being targeted. This allows for the programming interface to transmit the same amount of information every time in the same manner. Your design does not require all of the used information but it does require the “padded” file to program properly."

So my .bit file may not actually be a problem, which contradicts what the last service rep told me. Unfortunately, these kinds of responses are all I get to my problem and nothing further. It seems once they respond to the initial email with something rather generic, they're done. I'm hoping it's not a problem with the board but I'm not really able to verify that since they don't seem to want to help me resolve my issue. I've even offered to record a quick video of the entire process (which would only be around 5 min), talk with them over the phone, etc. and they've even ignored these attempts to help them help me!

 

[eemichael83]

My troubles are no more thanks to Alec from Digilent! He took the time to go through the steps I outlined as what I had been doing and got the same result with the same board. After a little investigation he found that the silkscreen print for the I/O on the board was wrong for the output I was trying to assign. He found the correct assignment and I tried that out and it worked as expected!

BTW all other emails exchanged before were also with Digilent, not Xilinx.