IMHO, Some inaccurate comments have been posted so far.
If you have an IRFxxx FET with Vt=2 to 4V , they can work well at 5V if your samples are near the 2V threshold, but this is a bad recommendation to use Vgs=5V for IRF series.
When parts are near the 4 V threshold you need 10V to compare with the spec for maxRdsOn. So the rule of Thumb is 2.5 times the max threshold voltage for minimum gate drive to be reliable. (10V/4V=2.5x) However on the sub-threshold types or "logic level FETs", this Rule of Thumb relaxes to Vgs= 2x threshold for minimum gate drive.
Also the IRFZ series is an excellent choice for logic level and the IRFZ44N is a popular low RdsOn logic level FET that "can be an excellent choice". But keep in mind RdsON * Coss = Tau tends to be constant in the same family or technology and voltage rating ,so when you choose really low Ron then it becomes a critical tradeoff with self lower resonant frequencies and losses increasing with switching rate.
Half-Bridge Dual-N Theory of Operation
1. The main requirement to work for the half-bridge with dual Nch FETs is to get the low-side PWM working to create the boost voltage needed above Vbus to greater the gate voltage for the high-side driver. check if Vgs = >=2.5 times Vt (250 uA threshold)
2. The damping losses for every part affect operation and efficiency. This means RdsOn, DCR of choke, and ESR of all caps. Too much total loop R, it falls overdamping. Too little it fails from high Q resonance, overshoot, and instability. So these are critical choices.
3. All control loops prefer 1st order feedback. This means current feedback for current error correction and voltage feedback for voltage error correction. However, the LTC4449 does not have current feedback inputs and all examples use a smart chip ahead of the drivers to take the current feedback signals to control the PWM. Without this, your dynamic performance will suffer. like step load response. Although 2nd order feedback can work with compensation to take a partial derivative of voltage feedback, it is not as good without current feedback.
4. Dead time is critical to check, so as not to cause shoot-thru currents and overheating. Too much dead-time then the flyback power duration increases. This is affected by junction temp and reactive loads. Consider 1<t< 10% of switch cycle.
these are my highlights. Good luck.
My best recommendation is follow a TI Webench design and or clone the kit layout and BOM parts. SMPS design is not trivial.
The Basso design book online is OK to use says the author to me. He welcomes the user feedback more than the publisher's revenue. This is possibly the best theory and practical book on SMPS design to date.
Also a schematic is not a "layout" of physical parts like a PCB, a schematic is a logic diagram and is missing all the parasitic analog parameters like 0.2 to 1.2 nH/mm or 0.05 to 0.5 pF stray capacitance or mutual inductance or mohms/cm resistance or ESR or DCR , decoupling caps, spectral impedance, dynamic load impedance etc .
