How can I fix VHDL errors related to declaration and array types?

[hong de]

library ieee;
use ieee.std_logic_1164.all;
entity miniproject is
port (dg1, dg2 : in std_logic_vector (3 downto 0);
led1, led2 : out std_logic_vector ( 6 downto 0);
output ut std_logic(6 downto 0));
end miniproject;
architecture arc of miniproject is
begin
with dg1 select
led1 <= "0010010" when "0010",
"1001100" when "0100",
"1111111" WHEN others;
with dg2 select
led2<= "0010010" when "0010",
"1001100" when "0100",
"1111111" WHEN others;


process( dg1,dg2 )
begin
if (dg1 = "0010" and dg2 = "0000") then
led1 <= '0' ; led2 <= '0' ;
elsif (dg1 = "0100" and dg2 = "0000") then
led1 <= '0' ; led2 <= '0' ;
else
led1 <= '1'; led2 <= '1';
end if;
end process;
end arc;

Error (10380): VHDL error at miniproject.vhd(6): std_logic type is used but not declared as an array type
Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings
Error: Processing ended: Tue Jul 26 09:21:14 2011
Error: Elapsed time: 00:00:02

 

[hong de]

The programme I want to do is using 8 inputs which represent 2 digits from 00 -99. Using 7- segments displays and Led1 and Led2 will light up when the values are "20" and "40". Hope you can help me.

 

[hong de]

Need help with my lab!

Question: 8 inputs are used to represent 2 digits from 00 to 99. Show the value on the 7-segment displays and the Led1 and Led2 will light up when the values are “20” and “40” respectively.

My answer:
library ieee;
use ieee.std_logic_1164.all;
entity miniproject is
port (dg1, dg2 : in std_logic_vector (3 downto 0);
led1, led2 : out std_logic_vector ( 6 downto 0);
output ut std_logic(6 downto 0));
end miniproject;
architecture arc of miniproject is
begin
with dg1 select
led1 <= "0010010" when "0010",
"1001100" when "0100",
"1111111" WHEN others;
with dg2 select
led2<= "0010010" when "0010",
"1001100" when "0100",
"1111111" WHEN others;


process( dg1,dg2 )
begin
if (dg1 = "0010" and dg2 = "0000") then
led1 <= '0' ; led2 <= '0' ;
elsif (dg1 = "0100" and dg2 = "0000") then
led1 <= '0' ; led2 <= '0' ;
else
led1 <= '1'; led2 <= '1';
end if;
end process;
end arc;

Error (10380): VHDL error at miniproject.vhd(6): std_logic type is used but not declared as an array type
Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings
Error: Processing ended: Tue Jul 26 09:21:14 2011
Error: Elapsed time: 00:00:02




What is wrong? can anyone help me?? THX in advance. (If possible Help me edit)

 

[jtbell]

Just out of curiosity, what language is this? I don't recognize it.

[added] OK, I see from the error message that it's VHDL. Carry on...

 

[KingNothing]

Perhaps you need to use "std_logic_vector" instead of "std_logic" in line 6 as you did in lines 4 and 5.