How can I understand whether an instruction is a fetch or read or

[kuchun]

How can I understand whether an instruction is a fetch or read or write instruction?..Please explain with examples of microprocessor 8085 instruction.
How can I count the no. of T states required by a particular 8085 microprocessor instruction?
Thank you

 

[rcgldr]

A "fetch" means the read cycle used to read the code bytes that make up an instruction. There isn't a "fetch" instruction. A "read" instruction is one that reads data from memory (like LDA), and a "write" instruction is one that writes data (like STA).

For the number of cycles for each instruction do a web search for "8085 opcode". Here's an example:

http://www.pastraiser.com/cpu/i8085/i8085_opcodes.html

Just curious, why the 8085? Are these still available?

 

[kuchun]

Thanks for your quick reply..I got the picture..But I have another question regarding the timing diagram of opcode fetch instruction:
We know that for the 1st T-state of the fetch cycle "ALE" signal remains high, thus enabling the AD0-AD7 to carry the lower order address.. But in the timing diagram the "ALE" signal is shown high only for a part of the 1st T-state, not for the total duration of the 1st T-state, whereas the AD0-AD7 lines carry the lower order memory address for the total duration of the 1st T-state..How is it possible?

 

[rcgldr]

Thanks for your quick reply..I got the picture..But I have another question regarding the timing diagram of opcode fetch instruction: We know that for the 1st T-state of the fetch cycle "ALE" signal remains high, thus enabling the AD0-AD7 to carry the lower order address.. But in the timing diagram the "ALE" signal is shown high only for a part of the 1st T-state, not for the total duration of the 1st T-state, whereas the AD0-AD7 lines carry the lower order memory address for the total duration of the 1st T-state..How is it possible?

This is an edge triggered device. The rising or falling edges of the primary clock drives everything else, with a slight delay, which may or may not be shown in these timing diagrams. ALE drops on the rising edge of the clock. The address lines are guaranteed to be set and stable when ALE drops, and that is when the 8085 latches used to hold an address are triggered. It doesn't matter when AD0-AD7 are dropped, as long as they are dropped long enough after ALE is dropped to not corrupt the address latches. AD0-AD7 are probably dropped on the next primary clock edge.

I don't know if an 8085 uses anyone shot delay circuits which can create delays independent of the primary clock. A one shot delay circuit relies on a fixed or programmable number of gate delays thorugh a series of transitors to generate a crude fixed pulse duration independent of the primary clock. These are not that accurate because gate delays can vary a bit from chip to chip.

 

[kuchun]

I want to know the timing diagram of CALL instruction in 8085..