How do I instantiate a full adder module in Verilog?

polaris90 · Mar 9, 2013

We are currently working with full adders in my logic circuits class.

I have the following code for a 4-bi full adder, however I'm having trouble understanding it and my textbook does a poor job at explaining the carry adders. fulladder f1(SW[5],SW[1],a,LEDG[1],b);this is the only line that I don't understand. I've seen this kind of code several times but no-one explains it. Can someone give a hand?

NascentOxygen · Mar 12, 2013

polaris90 said:

fulladder f1(SW[5],SW[1],a,LEDG[1],b);

this is the only line that I don't understand. I've seen this kind of code several times but no-one explains it. Can someone give a hand?

A google search turned up this: http://www.expertcore.org/viewtopic.php?t=767[/color]

I think that should help a bit.

How do I instantiate a full adder module in Verilog?

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