How do RS NAND latches work with feedback?

[springo]

Hi,
I'm trying to understand the basics of boolean logic gates and I'm stuck with latches. I think I don't really understand the concept of feedback or maybe it's something else but I haven't been able to understand how a basic RS NAND latch works.
Could somebody please explain it in simple words or give a link to an explanation?
Thank you very much in advance.
PS: http://www.play-hookey.com/digital/rs_nand_latch.html" is what I'm reading.

 

[xez]

Just draw out the truth table evolution
of the two cross linked gates and fill in the state changes
relative to the previous state affecting the subsequent
state affecting the new state of the gate with the initially
changed input and fill in the rest (the others that depend
on that output state transition) from there.

A NAND P = O
C NAND O = P
R = Rising
F = Falling

A has no control in this output state.
A P O C
H L H H
F L H H
L L H H

C has no control in this output state.
A P O C
H H L H
H H L F
H H L L

C = Active LOW SET of P
C = Active LOW RESET of O
A P O C
H L H H
H R F F
H H L L
H H L R
H H L H

A = ACTIVE LOW RESET OF P
A = ACTIVE LOW SET OF O
A P O C
H H L H
F F R H
L L H H

Just start with one gate's input transition,
transition that gate's output as apppopriate, take
that change and change any outputs that depend on it
as an input ... etc. and voila.

Hi,
I'm trying to understand the basics of boolean logic gates and I'm stuck with latches. I think I don't really understand the concept of feedback or maybe it's something else but I haven't been able to understand how a basic RS NAND latch works.
Could somebody please explain it in simple words or give a link to an explanation?
Thank you very much in advance.
PS: http://www.play-hookey.com/digital/rs_nand_latch.html" is what I'm reading.