JFET Biasing in Cascode: Designing a High Input Impedance Differential Amp

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Discussion Overview

The discussion revolves around the design of a high input impedance differential amplifier using JFETs, specifically focusing on the biasing of the first JFET in the circuit. Participants explore the implications of including or excluding a specific connection (referred to as the "blue wire") in the circuit design and its effects on DC offset and current flow.

Discussion Character

  • Technical explanation
  • Debate/contested
  • Mathematical reasoning

Main Points Raised

  • One participant expresses confusion about whether to include the blue wire in the circuit, noting that omitting it results in a DC offset while including it leads to minimal current through the bottom JFET and resistor.
  • Another participant suggests that the blue wire might short the input to the output, potentially explaining the removal of the offset.
  • A different participant recommends using high value resistors from the gate to the bottom of the bias resistor for both JFETs and suggests cutting the blue wire to add a 100 K resistor instead.
  • There is a question raised about whether this approach would drive the bottom JFET and bypass the gate on the top JFET, which could affect gain.
  • One participant shares a schematic of a TL081 JFET Opamp, possibly as a reference for the discussion.

Areas of Agreement / Disagreement

Participants express differing views on the role of the blue wire and the appropriate biasing strategy for the JFETs. The discussion remains unresolved regarding the best approach to achieve the desired performance without introducing DC offset.

Contextual Notes

There are limitations in the discussion regarding the assumptions made about the circuit configuration and the specific values of components used, which may affect the outcomes discussed.

SadScholar
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Hi, I'm trying to design a simple differential amp with extremely high input impedance. I'm using a couple of JFETs at the input stage to accomplish this. However, because I'm sending the signal from there to a differential amp, I don't want any DC offset, but I'm a little bit confused about how to bias J1, the first JFET. Basically my question is, should the blue wire be there. Even assuming I am dealing with two JFETs on the same silicon chip, and using the same value for both resistors, if I leave out that blue wire, I get a DC offset. But if I leave that blue wire in, I get almost no current through the bottom JFET and resistor, which is confusing to me. Any insight would be appreciated.
Here is the circuit diagram:
http://i516.photobucket.com/albums/u324/chrysolite13/CascodeCircuit.png
 
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SadScholar said:
Hi, I'm trying to design a simple differential amp with extremely high input impedance. I'm using a couple of JFETs at the input stage to accomplish this. However, because I'm sending the signal from there to a differential amp, I don't want any DC offset, but I'm a little bit confused about how to bias J1, the first JFET. Basically my question is, should the blue wire be there. Even assuming I am dealing with two JFETs on the same silicon chip, and using the same value for both resistors, if I leave out that blue wire, I get a DC offset. But if I leave that blue wire in, I get almost no current through the bottom JFET and resistor, which is confusing to me. Any insight would be appreciated.
Here is the circuit diagram:
http://i516.photobucket.com/albums/u324/chrysolite13/CascodeCircuit.png

Your blue wire would appear to short the input to the output, no?
 
Hah, that explains why it removes the offset.
 
There should be high value resistors from the gate to the bottom of the bias resistor for both FETS. So cut your blue wire and put a 100 K resistor in there.

But wouldn't you drive the bottom one and bypass the gate on the top one?

This would give more gain.
 
The attached is the schematic of TL081 JFET Opamp. Does that help?
 

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